TLV1562

2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL

CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN

SLAS162 – SEPTEMBER 1998

29

POST OFFICE BOX 655303

operating characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Before calibration

±5

After system calibration, single-ended input

±0.4

Mid-scale error (see Note 6)

After system calibration, differential input

±0.25

%FS

After internal calibration, single-ended input

±2.5

After internal calibration, differential input

±0.3

Offset error (see Note 6)

Before calibration

±5

%FS

Gain error (see Note 6)

Before calibration

±5

%FS

Total unadjusted error (see Note 7)

Before calibration

±5

%FS

Delay time, RD

↓, CSTART↑ to external

SYSCLK

↑, td(TRGL–ICLKH)

2ns

0.5

SYSCLK

Delay time, RD

↓ to start of conversion

td(RDL–CONV1)

2

ns

Internal OSC frequency

7.5

MHz

Delay time, RD

↑ to INT↑, td(RDH–INTZ) 1-kΩ pullup resistor, 10 pF, BDVDD = 5 V, use RD

10

ns

↑

At 25 pF, BDVDD = 5 V

4

↑

At 50 pF, BDVDD = 5 V

5

Disable time, RD

↑ to data invalid,

At 100 pF, BDVDD = 5 V

7

ns

,

,

tdis(DATAOUT)

At 25 pF, BDVDD = 2.7 V

7

ns

At 50 pF, BDVDD = 2.7 V

10

At 100 pF, BDVDD = 2.7 V

14

↓

At 25 pF, BDVDD = 5 V

20

↓

At 50 pF, BDVDD = 5 V

25

Enable time, INT

↓ to data valid,

At 100 pF, BDVDD = 5 V

30

ns

,

,

ten(DATAOUT)

At 25 pF, BDVDD = 2.7 V

37

ns

At 50 pF, BDVDD = 2.7 V

41

At 100 pF, BDVDD = 2.7 V

56

Delay time, mono interrupt mode pow-

Auto powerdown = 1

700

ns

y,

er-up time, t1(APDR)

Auto powerdown = 0

0

ns

Delay time, dual interrupt mode power-

Auto powerdown = 1

1000

ns

y,

up time, t2(APD)

Auto powerdown = 0

0

ns

Delay time INT

↓ to powerdown t(APD)

Auto powerdown = 1

200

ns

Delay time, INT

↓ to powerdown, t(APD)

Auto powerdown = 0

0

ns

Delay time, end of conversion to INT

↓,

td(CONV-INTL)

5

10

ns

Delay time, RD

↓ to INT Hi-Z,

td(RDL-INTZ)

1-k

Ω pullup resistor, 10 pF, BDVDD = 5 V, Use CSTART

10

ns

Delay time, CSTART

↑ to start of con-

version 1, td1(CSTARTH-CONV)

2

4

ns

Delay time, CSTART

↑ to start of con-

version 2, td2(CSTARTH-CONV)

0.2

1000

µs

Delay time, RD

↓ to sample,

td(RDL-SAMPLE)

2

SYSCLK

NOTES:

6. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference

between 111111111111 and the converted output for full-scale input voltage

7. Total unadjusted error comprises linearity, zero, and full-scale errors