TLV1572

2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTO-POWERDOWN

SLAS171A – DECEMBER 1997– REVISED SEPTEMBER 1998

2

POST OFFICE BOX 655303

functional block diagram

AIN

SCLK

FS

CS

DO

10-BIT

SAR ADC

CONTROL LOGIC

VCC

GND

VREF

GND

VREF

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CS/Powerdown

1

I

Chip Select. A low on this input enables the TLV1572. A high disables the device and disconnects the power

to the TLV1572.

AIN

2

I

Analog input

VREF

3

I

Reference voltage input. The voltage applied to this pin defines the input span of the TLV1572.

GND

4

Ground

DO

5

O

Serial data output. A/D conversion results are provided at this output pin.

FS

6

I

Frame sync input in DSP mode. The falling edge of the frame sync pulse from DSP indicates the start of

a serial data frame shifted out of the TLV1572. The FS input is tied to VCC when interfacing to a

micro-controller.

SCLK

7

I

Serial clock input. This clock synchronizes the serial data transfer and is also used for internal data

conversion.

VCC

8

Power supply, recommend connection to analog supply