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TLV2221 Datasheet(PDF) 26 Page - Texas Instruments |
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TLV2221 Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 29 page ![]() TLV2221, TLV2221Y Advanced LinCMOS ™ RAIL-TO-RAIL VERY LOW-POWER SINGLE OPERATIONAL AMPLIFIERS SLOS157A – JUNE 1996 – REVISED JANUARY 1997 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION driving large capacitive loads The TLV2221 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 49 through Figure 54 illustrate its ability to drive loads greater than 100 pF while maintaining good gain and phase margins (Rnull = 0). A small series resistor (Rnull) at the output of the device (Figure 55) improves the gain and phase margins when driving large capacitive loads. Figure 49 through Figure 52 show the effects of adding series resistances of 100 Ω, 200 Ω, 500 Ω, and 1 kΩ. The addition of this series resistor has two effects: the first effect is that it adds a zero to the transfer function and the second effect is that it reduces the frequency of the pole associated with the output load in the transfer function. The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To calculate the approximate improvement in phase margin, equation (1) can be used. ∆φ m1 + tan –1 2 × π × UGBW × R null × C L ∆φ m1 + improvement in phase margin UGBW + unity-gain bandwidth frequency R null + output series resistance C L + load capacitance (1) where : The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (Figure 53 and Figure 54). To use equation (1), UGBW must be approximated from Figure 53 and Figure 54. VDD – / GND VDD + Rnull CL VI + – RL Figure 55. Series-Resistance Circuit The TLV2221 is designed to provide better sinking and sourcing output currents than earlier CMOS rail-to-rail output devices. This device is specified to sink 500 µA and source 1 mA at VDD = 5 V at a maximum quiescent IDD of 200 µA. This provides a greater than 80% power efficiency. When driving heavy dc loads, such as 2 k Ω, the positive edge under slewing conditions can experience some distortion. This condition can be seen in Figure 37. This condition is affected by three factors: D Where the load is referenced. When the load is referenced to either rail, this condition does not occur. The distortion occurs only when the output signal swings through the point where the load is referenced. Figure 38 illustrates two 2-k Ω load conditions. The first load condition shows the distortion seen for a 2-kΩ load tied to 2.5 V. The third load condition in Figure 38 shows no distortion for a 2-k Ω load tied to 0 V. D Load resistance. As the load resistance increases, the distortion seen on the output decreases. Figure 38 illustrates the difference seen on the output for a 2-k Ω load and a 100-kΩ load with both tied to 2.5 V. D Input signal edge rate. Faster input edge rates for a step input result in more distortion than with slower input edge rates. |
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