TLV1571IPW datasheet(17/29 Pages) TI

17 / 29 page

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

simplified analog input analysis

Using the equivalent circuit in Figure 9, the time required to charge the analog input capacitance from 0 to VS

within 1/2 LSB, tch(1/2 LSB), can be derived as follows.

The capacitance charging voltage is given by:

Where:

Rt = Rs + Ri

Ri = Ri(ADC) + Ri(MUX)

tch = Charge time

C(t) +

1–e

–t

RtCi

The input impedance Ri is 718 Ω at 5 V, and is higher (~ 1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given

by:

VC (1/2 LSB) = VS – (VS/2048)

Equating equation 1 to equation 2 and solving for cycle time tc gives:

and time to change to 1/2 LSB (minimum sampling time) is:

tch (1/2 LSB) = Rt × Ci × ln(2048)

S *

2048

+ V

1–e

–t

RtCi

Where:

ln(2048) = 7.625

Therefore, with the values given, the time for the analog input signal to settle is:

tch (1/2 LSB) = (Rs + 718 Ω) × 15 pF × ln(2048)

This time must be less than the converter sample time shown in the timing diagrams, which is 6x SCLK.

tch (1/2 LSB) ≤ 6x 1/f(SCLK)

Therefore the maximum SCLK frequency is:

Max(f(SCLK)) = 6/tch (1/2 LSB) = 6/(ln(2048) × Rt × Ci)

(1)

(2)

(3)

(4)

(5)

(6)

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