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TLV2332IPWLE Datasheet(PDF) 25 Page - Texas Instruments |
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TLV2332IPWLE Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 33 page ![]() TLV2332, TLV2332Y, TLV2334, TLV2334Y LinCMOS ™ LOW-VOLTAGE MEDIUM-POWER OPERATIONAL AMPLIFIERS SLOS189 – FEBRUARY 1997 25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION single-supply operation (continued) The TLE2426 supplies an accurate voltage equal to VDD/2, while consuming very little power and is suitable for supply voltages of greater than 4 V. The TLV233x works well in conjunction with digital logic; however, when powering both linear devices and digital logic from the same power supply, the following precautions are recommended: • Power the linear devices from separate bypassed supply lines (see Figure 40); otherwise, the linear device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic. • Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive decoupling is often adequate; however, RC decoupling may be necessary in high-frequency applications. – + Logic Logic Logic Power Supply – + Logic Logic Logic Power Supply (a) COMMON-SUPPLY RAILS (b) SEPARATE-BYPASSED SUPPLY RAILS (preferred) Figure 40. Common Versus Separate Supply Rails input characteristics The TLV233x is specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially in single-supply operation. The lower the range limit includes the negative rail, while the upper range limit is specified at VDD – 1 V at TA = 25°C and at VDD – 1.2 V at all other temperatures. The use of the polysilicon-gate process and the careful input circuit design gives the TLV233x very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of operation. Because of the extremely high input impedance and resulting low bias-current requirements, the TLV233x is well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed bias-current requirements and cause a degradation in device performance. |
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