TLV2541 datasheet(23/26 Pages) TI

23 / 26 page

TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245 –MARCH 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

maximum conversion throughput (continued)

The maximum SCLK frequency possible is 12/tch 1

LSB = 44 MHz. Then a 20 MHz clock (maximum SCLK

frequency allowed for the internal comparator can be used. The minimum total cycle time is then reduced to:

(

cycle) + t(sample) ) tc ) t(overhead) +

max f (SCLK)

) 3.5 ms ) 0.1 ms + 4.4 ms

The maximum throughput is 1/4.4

µs = 227 KSPS for this case.

VI = Input Voltage at AIN

VS= External Driving Source Voltage

RS= Source Resistance

ri = Input Resistance (Mux On Resistance)

Ci = Input Capacitance

VC = Capacitance Charging Voltage

Driving Source Requirements:

Data Converter

Driving Source

ts AMP

NOTE: Noise and distortion must for the source be equivalent to the resolution of the converter.

Rs must be real at the input frequency.

Figure 31. Equivalent Input Circuit Including the Driving Source

power down calculations

Total power consumption at different conversion rate fs, (fs ≤ MAX [fs]) can be calculated by:

VDD × i(AVERAGE) = VDD [(fS/MAX [fs]) × i(ON) + (1–fs/MAX [fs]) × i(OFF)]

If VDD = 2.7 V for TLV2541, and the sampling rate fs = 10 kHz, the maximum sampling rate f(SMAX) = 200 kHz

then i(ON) = ~1 mA operating current

and i(OFF) = ~2

µA autopower-down current

so VDD × i(AVERAGE) = 2.7 × (0.05 × 1000 µA + 0.95 × 2 µA)

= (2.7

× 51.9) µW

= 140

µW

TLV2541 Datasheet(PDF) 23 Page - Texas Instruments

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