TLV2543C, TLV2543I

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS096B – MARCH 1995 – REVISED OCTOBER 1995

13

POST OFFICE BOX 655303

operating characteristics over recommended operating free-air temperature range,

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

EL

Linearity error (see Note 6)

See Figure 2

±1

LSB

ED

Differential linearity error

See Figure 2

±1

LSB

EO

Offset error (see Note 7)

See Note 2 and

Figure 2

±1.5

LSB

EG

Gain error (see Note 7)

See Note 2 and

Figure 2

±1

LSB

ET

Total unadjusted error (see Note 8)

±1.75

LSB

DATA INPUT = 1011

2038

2048

2058

Self-test output code (see Table 3 and Note 9)

DATA INPUT = 1100

0

10

DATA INPUT = 1101

4075

4095

tconv

Conversion time

See Figures 10 – 15

8

10

µs

tc

Total cycle time (access, sample, and conversion)

See Figures 10 – 15

and Note 10

10 + total

I/O CLOCK

periods +

td(I/O-EOC)

µs

tacq

Channel acquisition time (sample)

See Figures 10 – 15

and Note 10

4

12

I/O

CLOCK

periods

tv

Valid time, DATA OUT remains valid after I/O CLOCK

↓

See Figure 7

10

ns

td(I/O-DATA)

Delay time, I/O CLOCK

↓ to DATA OUT valid

See Figure 7

250

ns

td(I/O-EOC)

Delay time, last I/O CLOCK

↓ to EOC↓

See Figure 8

1.5

2.2

µs

td(EOC-DATA) Delay time, EOC↑ to DATA OUT (MSB / LSB)

See Figure 9

200

ns

tPZH, tPZL

Enable time, CS

↓ to DATA OUT (MSB/LSB driven)

See Figure 4

0.7

1.3

µs

tPHZ, tPLZ

Disable time, CS

↑ to DATA OUT (high impedance)

See Figure 4

70

150

ns

tr(EOC)

Rise time, EOC

See Figure 9

15

50

ns

tf(EOC)

Fall time, EOC

See Figure 8

15

50

ns

tr(bus)

Rise time, data bus

See Figure 7

15

50

ns

tf(bus)

Fall time, data bus

See Figure 7

15

50

ns

td(I/O-CS)

Delay time, last I/O CLOCK

↓ to CS↓ to abort conversion

(see Note 11)

5

µs

† All typical values are at TA = 25°C.

NOTES:

2. Analog input voltages greater than that applied to REF + convert as all ones (111111111111), while input voltages less than that

applied to REF – convert as all zeros (000000000000).

6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

7. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified

gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the

nominal midstep value at the offset point.

8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.

9. Both the input address and the output codes are expressed in positive logic.

10. I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7).

11. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at

≤ 5 µs

of the tenth I/O CLOCK falling edge to ensure that a conversion is aborted. Between 5

µs and 10 µs, the result is uncertain as to

whether the conversion is aborted or the conversion results are valid.