TLV2544CD datasheet(35/39 Pages) TI

35 / 39 page

TLV2544, TLV2548

2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN

SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

Driving Source†

TLV2544/48

VI = Input Voltage at AIN

VS = External Driving Source Voltage

Rs = Source Resistance

ri = Input Resistance (MUX on Resistance)

Ci = Input Capacitance

VC= Capacitance Charging Voltage

† Driving source requirements:

• Noise and distortion for the source must be equivalent to the resolution of the converter.

• Rs must be real at the input frequency.

Figure 39. Equivalent Input Circuit Including the Driving Source

maximum conversion throughput

For a supply voltage of 5 V, if the source impedance is less than 1 k

Ω, and the ADC analog input capacitance

Ci is less than 50 pF, this equates to a minimum sampling time tch(0.5 LSB) of 0.676

µs (t1µs). Since the

sampling time requires 12 SCLKs, the fastest SCLK frequency is 12/tch = 12 MHz.

The minimal total cycle time is given as:

+ tcommand ) tch ) tconv ) td(EOCH–CSL) + 4

f (SCLK)

) 12

f (SCLK)

) 3.6 ms ) 0.1 ms

+ 16

MHz

) 3.7 ms + 5.03 ms

This is equivalent to a maximum throughput of 200 KSPS. The throughput can be even higher with a smaller

source impedance.

When source impedance is 100

Ω, the minimum sampling time becomes:

tch (1 2 LSB)

+ Rt

In(8192)

+ 0.27 ms

The maximum SCLK frequency possible is 12/tch = 44 MHz. Then a 20 MHz clock (maximum SCLK frequency

for the TLV2544/2548 ) can be used. The minimal total cycle time is then reduced to:

+ tcommand ) tch ) tconv ) td(EOCH–CSL) + 4

f (SCLK)

) 12

f (SCLK)

) 3.6 ms ) 0.1 ms

+ 0.8 ms ) 3.6 ms ) 0.1 ms + 4.5 ms

The maximum throughput is 1/4.5

µs = 222 KSPS for this case.

TLV2544CD Datasheet(PDF) 35 Page - Texas Instruments

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