TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245 –MARCH 2000

7

POST OFFICE BOX 655303

timing diagrams/conversion cycles (continued)

OD8

SCLK

1

2

3

4

5

6

12

13

14

15

16

CS/FS

OD7

OD6

OD5

OD0

SDO

t(sample)

tc

t(powerdown)

7

OD9

1

OD10

OD9

OD11

OD10

OD11

Figure 5. TLV2545 Timing

use CS as FS input

When interfacing the TLV2541 with the TMS320 DSP, the FSR signal from the DSP may be connected to the

CS input if this is the only device on the serial port. This will save one output terminal from the DSP. (Output data

changes on the falling edge of SCLK. Default for TLV2542 and TLV2545).

SCLK and conversion speed

The minimum onboard oscillator frequency for the TLV2541/2/5 is 4 MHz, and it takes 14 conversion clocks to

complete the conversion. This leads to a 3.5

µs conversion time plus 0.1 µs overhead. These devices can

operate with an SCLK up to 20 MHz for the supply voltage range specified. The total conversion time is

14

= 4.4

µs for the TLV254x devices. This is the minimum cycle time for an active CS or CS/FS signal. If violated,

the conversion will terminate, invalidating the next data output cycle.

reference voltage

An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of

the positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital

is equal to or lower than GND.

powerdown and powerup initialization

Autopower down is built in to the devices in order to reduce power consumption. The wake-up time is fast

enough to provide power down between each cycle. The power-down state is initiated at the end of conversion

and wakes up upon a falling edge on CS or FS.