TLV320AC40IPT datasheet(19/23 Pages) TI

19 / 23 page

TLV320AC40, TLV320AC41

3-V VOICE-BAND AUDIO PROCESSORS (VBAP

™)

SLWS045A – JUNE 1996 – REVISED APRIL 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

output gain set design considerations (see Figure 7)

EARA and EARB are low-impedance complementary outputs. The voltages at the nodes are:

VO+ at EARA

VO– at EARB

VOD = VO+ – VO– (total differential response)

R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.

A value greater than 10 k

Ω and less than 100 kΩ for R1 + R2 is recommended because of the following:

The parallel combination R1 + R2 and RL sets the total loading. The total capacitance at EARGS and the

parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.

VA represents the maximum available digital mW output response (VA = 1.001 Vrms).

VOD = A × VA

where A =

1 + (R1/R2)

4 + (R1/R2)

Digital mW Sequence

IAW CCITT G.712

VO–

VO+

DIN

EARB

EARGS

EARA

NOTE A: Terminal numbers shown are for the DW and N packages.

Figure 7. Gain-Setting Configuration

higher clock frequencies and sample rates

The VBAP is designed to work with sample rates up to 16 kHz where the frequency of the frame sync determines

the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock

frequency, fCLK, to the frame sync frequency, fFSR/fFSX. This ratio for the VBAP is 1.152 MHz/8 kHz, or 144

master clocks per frame sync. For example, to operate the VBAP at a sampling rate of fFSR and fFSX equal to

16 kHz, fCLK must be 144 times 16 kHz, or 2.304 MHz. If the VBAP is operated above an 8-kHz sample rate,

however, it is expected that the performance becomes somewhat degraded. Exact parametric specifications

for rates up to 16-kHz sample rate are not specified at this time.

TLV320AC40IPT Datasheet(PDF) 19 Page - Texas Instruments