TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

2

POST OFFICE BOX 655303

functional block diagram

Power-On

Reset

Serial

Interface

× 2

DAC

DAC

× 2

× 2

DAC

DAC

× 2

LDAC

REFA

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

–

REFB

REFC

CLK

REFD

DATA

LOAD

DACA

DACB

DACC

DACD

8

8

8

8

8

8

8

8

Latch

Latch

Latch

Latch

Latch

Latch

Latch

Latch

2

3

4

5

7

6

8

13

12

11

10

9

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CLK

7

I

Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock

applied to the CLK terminal.

DACA

12

O

DAC A analog output

DACB

11

O

DAC B analog output

DACC

10

O

DAC C analog output

DACD

9

O

DAC D analog output

DATA

6

I

Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.

Each data bit is clocked into the register on the falling edge of the clock signal.

GND

1

I

Ground return and reference terminal

LDAC

13

I

Load DAC. When this signal is high, no DAC output updates occur when the input digital data is read into the serial

interface. The DAC outputs are only updated when LDAC is taken from high to low.

LOAD

8

I

Serial interface load control. When the LDAC terminal is low, the falling edge of the LOAD signal latches the digital

data into the output latch and immediately produces the analog voltage at the DAC output terminal.

REFA

2

I

Reference voltage input to DAC A. This voltage defines the output analog range.

REFB

3

I

Reference voltage input to DAC B. This voltage defines the analog output range.

REFC

4

I

Reference voltage input to DAC C. This voltage defines the analog output range.

REFD

5

I

Reference voltage input to DAC D. This voltage defines the analog output range.

VDD

14

I

Positive supply voltage