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TMS320C6201 Datasheet(PDF) 13 Page - Texas Instruments

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Part # TMS320C6201
Description  DIGITAL SIGNAL PROCESSORS
PDF  75 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320C6201 Datasheet(HTML) 13 Page - Texas Instruments

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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
13
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
†
NAME
GGP, GJC
PIN NO.
GJL
PIN NO.
TYPE†
DESCRIPTION
EMIF – SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SSADS
AC20
AD19
O/Z
SBSRAM address strobe
SSOE
AF21
AD18
O/Z
SBSRAM output enable
SSWE
AD19
AF18
O/Z
SBSRAM write enable
SSCLK
AD17
AC15
O
SBSRAM clock
EMIF – SYNCHRONOUS DRAM (SDRAM) CONTROL
SDA10
AD21
AC19
O/Z
SDRAM address 10 (separate for deactivate command)
SDRAS
AF24
AD21
O/Z
SDRAM row-address strobe
SDCAS
AD22
AC20
O/Z
SDRAM column-address strobe
SDWE
AF23
AE21
O/Z
SDRAM write enable
SDCLK
AE20
AC17
O
SDRAM clock
EMIF – BUS ARBITRATION
HOLD
AA25
Y25
I
Hold request from the host
HOLDA
A7
C9
O
Hold-request acknowledge to the host
TIMERS
TOUT1
H24
K23
O
Timer 1 or general-purpose output
TINP1
K24
L23
I
Timer 1 or general-purpose input
TOUT0
M4
M4
O
Timer 0 or general-purpose output
TINP0
K4
H2
I
Timer 0 or general-purpose input
DMA ACTION COMPLETE STATUS
DMAC3
D2
E1
DMAC2
F4
F2
O
DMA action complete
DMAC1
D1
G3
O
DMA action complete
DMAC0
E2
H4
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1
E25
F26
I
External clock source (as opposed to internal)
CLKR1
H23
H25
I/O/Z
Receive clock
CLKX1
F26
J24
I/O/Z
Transmit clock
DR1
D26
H23
I
Receive data
DX1
G23
G25
O/Z
Transmit data
FSR1
E26
J23
I/O/Z
Receive frame sync
FSX1
F25
G26
I/O/Z
Transmit frame sync
† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground



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