TMS320C6701 datasheet(39/70 Pages) TI

39 / 70 page

TMS320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SPRS067F − MAY 1998 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 18)

NO.

C6701-120

C6701-150

C6701-167

UNIT

MIN

MAX

tsu(EDV-SSCLKH)

Setup time, read EDx valid before SSCLK high

3.6

th(SSCLKH-EDV)

Hold time, read EDx valid after SSCLK high

1.5

switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK)

(see Figure 18 and Figure 19)

NO.

PARAMETER

C6701-120

C6701-150

C6701-167

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

tosu(CEV-SSCLKH)

Output setup time, CEx valid before SSCLK high

1.5P − 4.5

toh(SSCLKH-CEV)

Output hold time, CEx valid after SSCLK high

0.5P − 2.5

0.5P − 2

tosu(BEV-SSCLKH)

Output setup time, BEx valid before SSCLK high

1.5P − 4.5

toh(SSCLKH-BEIV)

Output hold time, BEx invalid after SSCLK high

0.5P − 2.5

0.5P − 2

tosu(EAV-SSCLKH)

Output setup time, EAx valid before SSCLK high

1.5P − 4.5

toh(SSCLKH-EAIV)

Output hold time, EAx invalid after SSCLK high

0.5P − 2.5

0.5P − 2

tosu(ADSV-SSCLKH)

Output setup time, SSADS valid before SSCLK high

1.5P − 4.5

toh(SSCLKH-ADSV)

Output hold time, SSADS valid after SSCLK high

0.5P − 2.5

0.5P − 2

tosu(OEV-SSCLKH)

Output setup time, SSOE valid before SSCLK high

1.5P − 4.5

toh(SSCLKH-OEV)

Output hold time, SSOE valid after SSCLK high

0.5P − 2.5

0.5P − 2

tosu(EDV-SSCLKH)

Output setup time, EDx valid before SSCLK high

1.5P − 4.5

toh(SSCLKH-EDIV)

Output hold time, EDx invalid after SSCLK high

0.5P − 2.5

0.5P − 2

tosu(WEV-SSCLKH)

Output setup time, SSWE valid before SSCLK high

1.5P − 4.5

toh(SSCLKH-WEV)

Output hold time, SSWE valid after SSCLK high

0.5P − 2.5

0.5P − 2

† When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For CLKMODE x1:

1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.

0.5P = PL, where PL = pulse duration of CLKIN low.

TMS320C6701 Datasheet(PDF) 39 Page - Texas Instruments

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