TMS320LC2402 datasheet(12/106 Pages) TI

12 / 106 page

TMS320LF2407, TMS320LF2406, TMS320LF2402

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C – APRIL 1999 – REVISED OCTOBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

pin functions (continued)

Table 2. ’LF240x and ’LC240x Pin List and Package Options†‡ (Continued)

PIN NAME

’LF2407

’2406

’LC2404

’2402

DESCRIPTION

ADDRESS, DATA, AND MEMORY CONTROL SIGNALS

Data space strobe. IS, DS, and PS are always high

unless low-level asserted for access to the relevant

external memory space or I/O. They are placed in the

high-impedance state during reset, power down, and

when EMU1/OFF is active low.

I/O space strobe. IS, DS, and PS are always high

unless low-level asserted for access to the relevant

external memory space or I/O. They are placed in the

high-impedance state during reset, power down, and

when EMU1/OFF is active low.

Program space strobe. IS, DS, and PS are always

high unless low-level asserted for access to the

relevant external memory space or I/O. They are

placed in the high-impedance state during reset,

power down, and when EMU1/OFF is active low.

R/W

Read/write qualifier signal. R/W indicates transfer

direction during communication to an external device.

It is normally in read mode (high), unless low level is

asserted for performing a write operation. It is placed

in the high-impedance state when EMU1/OFF is

active low and during power down.

W/R / IOPC0

W/R

Write/Read qualifier or GPIO. This is an inverted R/W

signal useful for zero-wait-state memory interface. It

is normally low unless a memory write operation is

W/R / IOPC0

IOPC0

is normally low, unless a memory write operation is

performed. See Table 13, Port C section, for reset

note regarding ’LF2406 and ’LF2402.

(

↑)

Read enable strobe. Read-select indicates an active,

external read cycle. RD is active on all external

program, data, and I / O reads. RD goes into the

high-impedance state when EMU1/OFF is active low.

Write enable strobe. The falling edge of WE indicates

that the device is driving the external data bus

(D15 – D0). WE is active on all external program,

data, and I/O writes. WE goes in the high-impedance

state when EMU1/OFF is active low.

STRB

External memory access strobe. STRB is always high

unless asserted low to indicate an external bus cycle.

STRB is active for all off-chip accesses. It is placed in

the high-impedance state during power down, and

when EMU1/OFF is active low.

READY

120

READY is pulled low to add wait states for external

accesses. READY indicates that an external device is

prepared for a bus transaction to be completed. If the

device is not ready, it pulls the READY pin low. The

processor waits one cycle and checks READY again.

Note that the processor performs READY-detection if

at least one software wait state is programmed. To

meet the external READY timings, the wait-state

generator control register (WSGR) should be

programmed for at least one wait state.

(

↑)

† Bold, italicized pin names indicate pin function after reset.

‡ GPIO – General-purpose input/output pin. All GPIOs come up as input after reset.

LEGEND:

↑ – Internal pullup

↓ – Internal pulldown

TMS320LC2402 Datasheet(PDF) 12 Page - Texas Instruments

TMS320LC2402 Datasheet(HTML) 12 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL