TMS77C82 datasheet(24/49 Pages) TI

24 / 49 page

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

programmable timer 1 (continued)

D Hard watchdog configuration (see Figure 9) – for mask-ROM devices:

–

Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK

–

A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

–

Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows.

–

Automatic activation of the WD timer upon power-up reset

–

INT1 is enabled as a nonmaskable interrupt during low-power modes.

–

A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.5

WD OVRFL

INT FLAG

Figure 9. Hard Watchdog

D Simple counter configuration – for mask-ROM devices only (see Figure 10)

–

Simple counter can be configured as an event counter, pulse accumulator, or an internal timer.

TMS77C82 Datasheet(PDF) 24 Page - Texas Instruments