TMS77C82 datasheet(28/60 Pages) TI

28 / 60 page

TMS370Cx2x

8-BIT MICROCONTROLLER

SPNS018C – FEBRUARY 1993 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

serial peripheral interface (continued)

D Transmitter and receiver operations occur through interrupt-driven or polled algorithms.

D Seven SPI module control registers located in control register frame beginning at address P030h

The SPI module control registers are listed in Table 15.

Table 15. SPI Module Control Register Memory Map

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

P030

SPI SW

RESET

CLOCK

POLARITY

SPI BIT

RATE2

SPI BIT

RATE1

SPI BIT

RATE0

SPI

CHAR2

SPI

CHAR1

SPI

CHAR0

SPICCR

P031

RECEIVER

OVERRUN

SPI INT

FLAG

—

MASTER/

SLAVE

TALK

SPI INT

ENA

SPICTL

P032

P036

Reserved

P037

RCVD7

RCVD6

RCVD5

RCVD4

RCVD3

RCVD2

RCVD1

RCVD0

SPIBUF

P038

Reserved

P039

SDAT7

SDAT6

SDAT5

SDAT4

SDAT3

SDAT2

SDAT1

SDAT0

SPIDAT

P03A

P03C

Reserved

P03D

—

SPICLK

DATA IN

SPICLK

DATA OUT

SPICLK

FUNCTION

SPICLK

DATA DIR

SPIPC1

P03E

SPISIMO

DATA IN

SPISIMO

DATA OUT

SPISIMO

FUNCTION

SPISIMO

DATA DIR

SPISOMI

DATA IN

SPISOMI

DATA OUT

SPISOMI

FUNCTION

SPISOMI

DATA DIR

SPIPC2

P03F

SPI

STEST

SPI

PRIORITY

SPI

ESPEN

—

SPIPRI

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