TMS44400, TMS44400P, TMS46400, TMS46400P

1048576-WORD BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORIES

SMHS562C – MAY 1995 – REVISED NOVEMBER 1996

17

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

tRASP

tRP

RAS

CAS

A0 – A9

W

DQ1 – DQ4

OE

tCSH

tPRWC

tRCD

tCAS

tRSH

tCRP

tCP

tASR

tASC

tAR

tRAD

tCAH

Row

Column

Column

Don’t Care

tCWL

tRWL

tRAH

tCWD

tAWD

tRWD

tWP

tRCS

tAA

tRAC

tCAC

tCPA

tDH

Valid Out

(see Note A)

Valid Out

Valid In

Valid In

tCLZ

tOEA

tOEZ

tOEH

tOED

tOEH

tDS

NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.

B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.

Figure 10. Enhanced-Page-Mode Read-Write-Cycle Timing