TP3054B, TP3057B, TP13054B, TP13057B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS042A – MAY 1990 – REVISED JULY 1996

14

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

asynchronous operation

For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must

be 2.048 MHz for the TP3057B and TP13057B, 1.536 MHz or 1.544 MHz for the TP3054B and TP13054B and

need not be synchronous. However, for best performance, MCLKR should be synchronous with MCLKX. This

is easily achieved by applying only static logic levels to MCLKR/PDN. This connects MCLKX to all internal

MCLKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame.

Each encoding cycle is started with FSX and FSX must be synchronous with MCLKX and BCLKX. Each

decoding cycle is started with FSR and FSR must be synchronous with BCLKR. The logic levels shown in

Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from 64 kHz to 2.048 MHz.

short-frame sync operation

The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically

goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing

relationships specified in Figure 1. With FSX high during a falling edge of BCLKX, the next rising edge of BCLKX

enables the 3-state output buffer, DX, which outputs the sign bits. The remaining seven bits are clocked out on

the following seven rising edges and the next falling edge disables DX. With FSR high during a falling edge of

BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following

seven falling edges latch in the seven remaining bits. The short-frame sync pulse may be utilized in either the

synchronous or asynchronous mode.

long-frame sync operation

Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing

relationships as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a short-

or long-frame sync pulse is being used. For 64-kHz operation, the frame-sync pulse must be kept low for a

minimum of 160 ns. The rising edge of FSX or BCLKX, which ever occurs later, enables the DX 3-state output

buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the

remaining seven bits. The falling edge of BCLKX following the eighth rising edge or FSX going low, whichever

occurs later, disables DX. A rising edge on FSR, the receive-frame sync pulse, causes the PCM data at DR to

be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync

pulse can be utilized in either the synchronous or asynchronous mode.

transmit section

The transmit section input is an operational amplifier with provision for gain adjustment using two external

resistors. The low noise and wide bandwidth characteristics of these devices provide gains in excess of 20 dB

across the audio passband. The operational amplifier drives a unity-gain filter consisting of an RC active prefilter

followed by an eighth-order switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter

directly drives the encoder sample-and-hold circuit. As per

µ-law (TP3054B and TP13054B) or A-law (TP3057B

and TP13057B) coding conventions, the ADC is a companding type. A precision voltage reference provides a

nominal input overload of 2.5 V peak. The sampling of the filter output is controlled by the FSX frame-sync pulse.

Then the successive-approximation encoding cycle begins. The 8-bit code is loaded into a buffer and shifted

out through DX at the next FSX pulse. The total encoding delay is approximately 290

µs. Any offset voltage due

to the filters or comparator is cancelled by sign-bit integration.