TP3056B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SLWS072A – MAY 1998 – REVISED AUGUST 1998

13

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

system reliability and design considerations

TP3056B system reliability and design considerations are described in the following paragraphs.

latch-up

Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the

inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will

continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device

if supply current to the device is not limited.

Even though the TP3056B is heavily protected against latch-up, it is still possible to cause latch-up under certain

conditions in which excess current is forced into or out of one or more terminals. Latch-up can occur when the

positive supply voltage drops momentarily below ground, when the negative supply voltage rises momentarily

above ground, or possibly if a signal is applied to a terminal after power has been applied but before the ground

is connected. This can happen if the device is hot-inserted into a card with the power applied, or if the device

is mounted on a card that has an edge connector and the card is hot-inserted into a system with the power on.

To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased

Schottky diode with a forward voltage drop of less than or equal to 0.4 V (1N5711 or equivalent) between the

power supply and GND (see Figure 3). If it is possible that a TP3056B-equipped card that has an edge connector

could be hot-inserted into a powered-up system, it is also important to ensure that the ground edge connector

traces are longer than the power and signal traces so that the card ground is always the first to make contact.

VCC

DGND

VBB

Figure 3. Latch-Up Protection Diode Connection