TSB12C01APZ datasheet(29/59 Pages) TI

29 / 59 page

3–13

3.3.5

RAM Test Mode

The purpose of RAM test mode is to test the RAM with writes and reads. During RAM test mode, RAM, which

makes up the ATF, ITF, and GRF, is accessed directly from the host bus. Different data is written to and read

back from the RAM and compared with what was expected to be read back. ATF status, ITF status, and GRF

status are not changed during RAM test mode, but the stored data in RAM is changed by any write

transaction. To enable RAM test mode, set regRW bit and RAMTest bit of the diagnostics register. Before

beginning any read or write to the RAM, the Adr_clr bit of the diagnostics register should be set to clear the

internal RAM address counter. This action also clears the Adr_clr bit.

During RAM test mode, the host bus address should be 80h. The first host bus transaction (either read or

write) accesses location 0 of the RAM. The second host bus transaction accesses location 1 of the RAM.

The nth host bus transaction accesses location n–1 of the RAM. After each transaction, the internal RAM

address counter is incremented by one.

The RAM has 512 locations with each location containing 33 bits. The most significant bit is the control bit.

When the control bit is set, that indicates the quadlet is the start of the packet. In order to set the control bit,

Control-bit1 of the diagnostics register has to be set. In order to clear the control bit, Control_bit1 of the

diagnostics register has to be cleared. When a write occurs, the 32 bits of data from the host bus is written

to the low order 32 bits of the RAM and the value in Control-bit1 is written to the control bit. When a read

occurs, the low order 32 bits of RAM are sent to the host data bus and the control bit is compared to

Control_bit1. If the control bit and Control_bit1 do not match, Control_bit_err of the diagnostics register is

set. This does not stop operation and another read or write can immediately be transmitted. To clear

Control_bit_err, set Adr_clr of the diagnostics register, or transact another write.

TSB12C01APZ Datasheet(PDF) 29 Page - Texas Instruments