TSB14C01

5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER

SLLS231B – MARCH 1996 – REVISED MAY 1997

19

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

definition of logic states

Drivers assert the bus to indicate a 1 logic state, or release the bus to indicate a 0 logic state. To assert the bus,

a driver sinks current. To release the bus, drivers are asserted to a high-impedance state or turned off, allowing

the bus signal to be pulled to the termination voltage of the bus.

NOTE

This typically results in a logical inversion of signals on TTL and BTL buses. Signals on ECL buses

typically are not inverted.

All drivers operate in a wired-ORed or open-collector mode during arbitration. Drivers can operate in a totem

pole mode during data packet and acknowledge transfers. In this mode, a driver can drive the bus into its

released state in order to decrease the rise time of the bus signal (referred to as a rescinding release with TTL

technology).

bit rates

Data transmission and reception occurs at 49.152 Mbit/s or 98.304 Mbit/s (

±100 ppm). Regardless of the

interface technology, arbitration occurs at an arbitration clock rate of 49.152 MHz.

backplane transmit data timing

Edge separation is the minimum required time between any two consecutive transitions of the backplane bus

signals, as they appear from the output of the transmitters, whether they be transitions on the same signal or

transitions on the two separate signals. A minimum edge separation is required to ensure proper operation of

the data strobe bit-level encoding mechanism. TDATA and TSTRB have the relationship shown in Figure 9 and

Table 13.

t1

t1

t1

t1

t2

t2

t2

t2

TDATA

TSTRB

Figure 9. Minimum Edge Separation

Table 13. TSB14C01 to Backplane Transceiver Timing

PARAMETER

98.304 MHz

49.152 MHz

t1

Bit cell period for data

10.1715 ns minimum

20.3430 ns minimum

t2†

Transmit (Tx) edge separation

8.1715 ns minimum

18.3430 ns minimum

† This parameter is based on a maximum total transmit skew of 2 ns