TSB41LV03A, TSB41LV03AI

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

13

POST OFFICE BOX 655303

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)

(continued)

device

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

See Note 3

163

IDD

Supply current

See Note 4

122

mA

See Note 5

104

IDD–ULP Supply current – ultra low power mode

VDD = 3.3 V,

TA = 25°C,

Ports disabled,

PD=0V, LPS=0V

150

µA

VTH

Power status threshold, CPS input†

400–k

Ω resistor†

4.7

7.5

V

VOH

High-level output voltage, CTL0, CTL1,

VDD=2.7 V,

IOH = –4 mA

2.2

V

VOH

g

g ,,,

D0–D7, CNA, C/LKON, SYSCLK outputs

VDD=3 to 3.6 V, IOH = –4 mA

2.8

V

VOL

Low-level output voltage, CTL0, CTL1,

D0–D7, CNA, C/LKON, SYSCLK outputs

IOL = 4 mA

0.4

V

VOH–AJ

High-level Annex J output voltage, CTL0,

CTL1, D0–D7, C/LKON, SYSCLK outputs

Annex J: IOH= –9 mA,

/ISO = 0V,

VDD_5V = VDD

VDD ≥ 3.0V

VDD–0.4

V

VOL–AJ

Low-level Annex J output voltage, CTL0,

CTL1, D0–D7, C/LKON, SYSCLK outputs

Annex J: IOL= 9 mA,

/ISO = 0V,

VDD_5V = VDD

VDD ≥ 3.0V

0.4

V

IBH+

Positive peak bus holder current, D0–D7,

CTL0–CTL1, LREQ

/ISO = 3.6V,

VDD = 3.6V,

VI = 0 V to VDD,VDD_5V = VDD

0.05

1

mA

IBH–

Negative peak bus holder current, D0–D7,

CTL0–CTL1, LREQ

ISO = 3.6V,

VDD = 3.6V,

VI = 0 V to VDD,VDD_5V = VDD

–1.0

–0.05

mA

II

Input current, LREQ, LPS, PD, TESTM, SM,

PC0–PC2 inputs

/ISO=0V, VDD = 3.6 V

1

µA

IOZ

Off-state output current, CTL0, CTL1,

D0–D7, C/LKON I/O’s

VO = VDD or 0 V

±5

µA

IIRST

Pullup current /RESET input

VI =15Vor0V

TSB41LV03A

–90

–20

µA

IIRST

Pullup current, /RESET input

VI = 1.5 V or 0 V

TSB41LV03AI

–100

–20

µA

ISE–PU

Pullup current, SE input

VI = 1.5 V or 0 V

–50

–5

µA

VIT+

Positive input threshold voltage, LREQ,

CTL0, CTL1, D0–D7 inputs‡

VDD_5V=VDD, ISO= 0 V

VDD/2+0.3

VDD/2+0.9

V

Positive input threshold voltage, LPS inputs

VDD_5V=VDD /ISO= 0 V,

Vref=VDD × 0.42

Vref+1

V

VIT–

Negative input threshold voltage, LREQ,

CTL0, CTL1, D0–D7 inputs‡

/ISO= 0 V,

VDD_5V=VDD

VDD/2–0.9

VDD/2–0.3

V

Negative input threshold voltage, LPS

inputs

/ISO= 0 V,

VDD_5V=VDD,

Vref=VDD × 0.42

Vref+0.2

V

VO

TPBIAS output voltage

At rated IO current

1.665

2.015

V

† Measured at cable power side of resistor.

‡ This parameter applicable only when ISO low.

NOTES:

3. Transmit Max Packet (3 ports transmitting max size isochronous packet – 4096 bytes, sent on every isochronous interval, s400,

data value of 0xCCCCCCCCh), VDD= 3.3 V, TA=25°C

4. Repeat typical packet (1 port receiving DV packets on every isochronous interval, 2 ports repeating the packet, s100), VDD = 3.3 V,

TA= 25°C

5. Idle (3 ports transmitting cycle starts), VDD = 3.3 V, TA = 25°C