TUSB2036

2/3-PORT HUB FOR THE UNIVERSAL SERIAL BUS

WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS372 – MARCH 2000

6

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

VF

I/O

DESCRIPTION

PWRON1 –

PWRON3

9, 13,

17

O

Power-on/-off control signals. PWRON1 – PWRON3 are active low, push-pull outputs. Push-pull outputs

eliminate the pullup resistors which open-drain outputs require. However, the external power switches that

connect to these pins must be able to operate with 3.3-V inputs because these outputs cannot drive 5-V

signals.

RESET

4

I

Reset. RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET

is asserted, all logic is initialized. Generally, a reset with a pulse width between 100

µs and 1 ms is

recommended after 3.3-V VCC reaching its 90%. The clock signal must be active during the last 60 µs of the

reset window.

SUSPND

32

O

Suspend status. SUSPND is an active high output available for external logic power-down operations. During

the suspend mode, SUSPND is high. SUSPND is low for normal operation.

MODE

31

I

Mode select. When MODE is low, the APLL output clock is selected as the clock source to drive the internal

core of the chip and 6-MHz crystal or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48

is selected as the clock source and 48-MHz oscillator or other on-board clock source can be used.

NP3

24

I

Number of ports is 3. Active low input. A logic 0 configures the system to use 3 ports. A logic 1, configures

the system to use 2 ports.

NPINT1–0

23, 22

I

Number of ports internal to hub system, which are permanently attached (see Table 1)

VCC

3, 25

3.3-V supply voltage

XTAL1/CLK48

30

I

Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty

cycle. An internal APLL generates the 48-MHz and 12-MHz clocks used internally by the ASIC logic. When

MODE is high, XTAL1/CLK48 acts as the input of the 48 MHz clock and the internal APLL logic is bypassed.

XTAL2

29

O

Crystal 2. XTAL2 is a 6-MHz crystal output. This terminal should be left open when using an oscillator.