TVP3030 datasheet(21/107 Pages) TI

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2–5

if the VGA port is used. This selects latching of VGA(7 – 0) and VGABL with CLK0. If CSR(2 – 0) = 000, CLK0

is also selected as the clock source to generate the internal dot clock. However, in this mode, MCR6 must

be logic 1 if the VGA port is used. This selects latching of VGA(7 – 0) and SYSBL with LCLK.

Additionally, two crystal oscillator terminals (XTAL1, XTAL2) are provided for the integrated pixel clock and

memory clock frequency synthesis PLLs. These terminals are intended for use with a quartz crystal

resonator, but a discrete oscillator can also be utilized and input on the XTAL2 terminal (XTAL1 terminal

should be left floating in this case).

Selection of the pixel clock PLL as the pixel clock source is performed by programming the clock selection

Table 2–5. Clock-Selection Register Bits CSR(3 – 0) (Index: 0x1A, Access: R/W, Default: 0x07)

CLOCK SELECT

FUNCTION

Select CLK0 as clock source (for use with LCLK latching of VGA port). See

Section 2.8.2.

Reserved

Select pixel clock PLL as clock source

Disable internal dot clock for reduced power consumption

Select CLK0 as clock source (for use with CLK0 latching of VGA port). See

Section 2.8.2.

Reserved

2.5

PLL Clock Generators

In addition to externally supplied clock sources, the TVP3030 has three on-chip, fully programmable,

frequency-synthesis phase-locked loops (PLLs). The first (pixel clock) PLL is intended for pixel clock

generation for frequencies up to the device limit. The second (MCLK) PLL is provided for general clocking

such as the system clock or memory clock, and the third PLL (called the loop clock PLL) is provided for

synchronizing pixel data and latch timing by compensating for system loop delay.

TVP3030 Datasheet(PDF) 21 Page - Texas Instruments