TVP3409 datasheet(21/57 Pages) TI

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2–9

2.2.10

Clock Synthesizer Register Sets

The clock synthesizer register sets determine the frequencies of clock synthesizer A (PLLA, OTCLKA) and

clock synthesizer B (PLLB, OTCLKB) for a given reference frequency. There are four sets for OTCLKA and

four sets for OTCLKB. A set of registers is chosen by toggling either the FS(1,0) terminals or the CC(5,4)

or CC(1,0) bits.

Each register set consists of four registers. The four registers have information affecting seven functions

of the clock synthesizer. The feedback divider term (M) together with the reference divider term (N) and

postscaler term (P) determine the frequency according to equation 1 in Section 2.6.4.1, Determining Output

Frequency. The M term is 8 bits, the N term is 6 bits, and the P term is 2 bits.

Table 2–12 and Table 2–14 show the fields associated with each term. The third and fourth registers are

reserved and can be read which returns the values written, but does not affect the function of the device.

The clock synthesizer A register sets are operational on power up. They can be read from or written to by

the MPU at any time and they are not initialized. All of the registers are reset to produce the frequencies in

Table 2–19 upon asserting RESET. To read from or write to these registers, set bit CR0(0) = 1, write

0x40 – 0x4F to the WMA, and set RS(1,0) = HL. These registers cannot be accessed by state machine

addressing (see Table 2–5 and Table 2–19).

Table 2–11. Clock Synthesizer A Parameters

CONTROL SET

ACCESS

NUMBER

DESCRIPTION

DEFAULT

FREQUENCY

Reserved

CC(5,4) = 00 or

None

25.057 MHz

Reserved

CC(5,4) = 00 or

FS(1,0) = LL

Reserved

CC(5,4) = 01 or

None

28.189 MHz

Reserved

CC(5,4) = 01 or

FS(1,0) = LH

AC0(7–0)

Feedback divider term (M)

AC1(7,6)

CC(5,4) = 10 or

Read or

Write

Postscaler divider term (P)

50.114 MHz

AC1(5–0)

CC(5,4) = 10 or

FS(1,0) = HL

Write

Reference divider term (N)

AD0(7–0)

Feedback divider term (M)

AD1(7,6)

CC(5,4) = 11 or

Read or

Write

Postscaler divider term (P)

75.170 MHz

AD1(5–0)

CC(5,4) = 11 or

FS(1,0) = HH

Write

Reference divider term (N)

Table 2–12. Clock Synthesizer A Register Set Fields

CLOCK REGISTER 0, BITS AND FIELDS

CLOCK REGISTER 1, BITS AND FIELDS

M(7–0)†

P(1,0)‡

N(5–0)§

CLOCK REGISTER 2, BITS AND FIELDS

CLOCK REGISTER 3, BITS AND FIELDS

Reserved

† M(7–0), 8 bits, integer from 0 to 255 (2 is added to this value)

‡ P(1,0), 2 bits, integer from 0 to 3 (these bits indicate the power of 2. See equation 1 in Section 2.5.4.1, Determining

Output Frequency)

§ N(5–0), 6 bits, integer from 0 to 63 (2 is added to this value)

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