TWL1109

VOICE-BAND AUDIO PROCESSOR (VBAP

™)

SLWS095 – MARCH 2000

21

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

DTMF generator operation and interface (continued)

Tones from the DTMF generator block are present at all outputs and are controlled by enabling or disabling the

individual output ports. The values that determine the tone frequency are loaded into the tone registers (high

and low) as two separate values.

The values loaded into the tone registers initiate an iterative table look-up function, placing a 6-bit or 7-bit in 2s

complement value into the the tone registers. There is a 2 dB difference in the resulting output of the two

registers, the high tone register having the greater result.

buzzer logic section

The single-ended output BUZZCON is a PDM signal intended to drive a buzzer through an external driver

transistor. The PDM begins as a selected DTMF tones, generated and passed through the receive D/A channel,

and fed back to the transmit channel analog modulator, where a PDM signal is generated and routed to the

BUZZCON output.

support section

The clock generator and control circuit use the master clock input (MCLK) to generate internal clocks to drive

internal counters, filters, and convertors. Register control data is written into and read back from the VBAP

registers via the control interface.

consists of the following terminals:

SCL:

SDA:

control addresses and data into and out of the codec. It is an open drain terminal and therefore

TWL1109 has a fixed device select address of {E2}HEX for write mode and {E3}HEX for read mode.

For normal data transfer, SDA is allowed to change only when SCL is low. Changes when SCL is high are

reserved for indicating the start and stop conditions.

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain

stable whenever the clock line is at high. Changes in the data line while the clock line is at high are interpreted

as a start or stop condition.

CONDITION

STATUS

DESCRIPTION

A

Bus not busy

Both data and clock lines remain at high

B

Start data transfer

A high to low transition of the SDA line while the clock (SCL) is high determines a start condition.

All commands must proceed from a start condition.

C

Stop data transfer

A low to high transition of the SDA line while the clock (SCL) is high determines a stop condition.

All operations must end with a stop condition.

D

Data valid

The state of the data line represents valid data when, after a start condition, the data line is stable

for the duration of the high period of the clock signal.