STA2500D datasheet(10/57 Pages) STMICROELECTRONICS

10 / 57 page

Quick reference data

STA2500D

10/57

Doc ID 16067 Rev 1

2.5

Current consumption

Tamb = 25°C, 13 MHz digital clock, 7 dBm output power for BR packets, 3 dBm output power

for EDR packets.

Vhyst

Schmitt trigger hysteresis (BT_VIO_B = 1.3 V)

0.2

0.3

0.4

CIN

Input capacitance

2.5

TRISE

10% - 90% rise time(1)

μs

TFALL

90% - 10% fall time(1)

μs

Total jitter(2)

250

ppm

The rise and fall time are not the most important parameters for the low power clock input due to the Schmitt trigger logic. It

is more important that the noise on the Low power clock line remains substantially below the hysteresis in amplitude.

The total jitter is defined as the error that can appear on the actual frequency between two clock edges compared to the

perfect frequency. Due to this, the total jitter value must contain the jitter itself and the error due to the accuracy on the

clock frequency. The lower the accuracy, the smaller the jitter is allowed to be.

Table 11.

Low power clock specifications (continued)

The low power clock pin is powered by connecting BT_VIO_B to the wanted supply.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Table 12.

Current consumption(1)

State

Typ.

Unit

Complete Power Down

μA

Deep Sleep mode

μA

Functional Sleep mode(2)

1.2

Sniff mode (1.28 s, 2 attempts, 0 timeouts), combined with H4 UART Deep Sleep

mode

(see section 6.10.3)

Master mode

Slave mode

μA

Inquiry scan (1.28 seconds period), combined with H4 UART Deep Sleep mode

(see section 6.10.3)

318

μA

HW Page scan (1.28 seconds period), combined with H4 UART Deep Sleep mode

(see section 6.10.3)

312

μA

HW Inquiry and Page scan (1.28 seconds period), combined with H4 UART Deep

Sleep mode

(see section 6.10.3)

591

μA

Idle ACL connection (Master)

3.6

Idle ACL connection (Slave)

8.2

Active: audio (HV3) Master (not sniffed)

11.7

Active: audio (HV3) Slave (Sniff 1.28 s, 2 attempts, 0 timeouts)

10.6

Active: data (DH1) Master or Slave

(172.8 kbps asymmetrical in TX mode)

(172.8 kbps symmetrical)

28.5

STA2500D Datasheet(PDF) 10 Page - STMicroelectronics

STA2500D Datasheet(HTML) 10 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Datasheet Download

Link URL