4

UC5350

0.5V

2.25V

2.75V

3.5V

4.5V

5V

∆ V6,7 = 1.5V (MIN)

∆ V6,7 = 3V (MAX)

Figure 4. Dominant State Voltage Diagram

—7V

—2V

0V

—6.1V

12V

BUS CMR (MAX)

5V

BUS CMR (MIN)

VDIFF(D) = 0.9V (MIN)

VDIFF(D) = 5V (MAX)

Figure 5. Dominant State Voltage Diagram

UDG-97161

TXD = LOGIC 0

is disconnected from the bus line; 60

in parallel with 100pF load between CANH and CANL. VCC = 4.5V to 5.5V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

TXD = 1V (Figure 4)

2.75

4.5

V

TXD = 1V (Figure 4)

0.50

1.1

2.25

V

1.5

2

3

V

Common Mode Range = –2 to +7V, TXD = 4V,

CANH, CANL Externally Driven (Figure 5)

0.9

5

V

Common Mode Range = –7 to +12V, TXD = 4V,

CANH, CANL Externally Driven (Figure 5)

1.0

5

V

UDG-97160

TRANSMITTER CHARACTERISTICS

Unless otherwise stated, the device is disconnected from the bus line; 60

Ω in

parallel with 100pF load between CANH and CANL.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Differential Output Transmitter

Dominant Mode

1.5

2

3

V

Recessive Mode

–500

50

mV

(Figure 6)

50

100

ns

Ω Across CANH and CANL (Figure 6)

20

110

ns