•

Complies with SCSI, SCSI-2 and

SPI-2 Standards

•

3pF Channel Capacitance during

Disconnect

•

100

µA Supply Current in

Disconnect Mode

•

Meets SCSI Hot Plugging Capability

•−400mA Sourcing Current for

Termination

•

+400mA Sinking Current for Active

Negation

•

Logic Command Disconnects all

Termination Lines

•

Trimmed Termination Current to 5%

•

Trimmed Impedance to 5%

•

Current Limit and Thermal

Shutdown Protection

The UC5613 provides 9 lines of active termination for a SCSI (Small Com-

puter Systems Interface) parallel bus. The SCSI standard recommends ac-

tive termination at both ends of the cable segment.

The UC5613 provides a disconnect feature which, when opened or driven

high, disconnects all terminating resistors and disables the regulator

greatly reducing standby power. The output channels remain high imped-

ance even without Termpwr applied. A low channel capacitance of 3pF al-

lows units at interim points of the bus to have little or no effect on the signal

integrity.

The UC5613 is pin-for-pin compatible with its predecessor, the UC5603 - 9

line Active Terminator. The only functional difference between the UC5613

and UC5603 is the absence of the negative clamps. Parametrically, the

UC5613 has a 5% tolerance on impedance and current compared to a 3%

tolerance on the UC5603. Custom power packages are utilized to allow

normal operation at full power (1.2 watts).

Internal circuit trimming is utilized, first to trim the impedance to a 5% toler-

ance; then, the output current is trimmed to a 5% tolerance. The output

current trim is set as close as possible to the maximum value of the SCSI

specification which maximizes the noise margin for fast SCSI operation.

Other features include thermal shutdown and current limit.

This device is offered in low thermal resistance versions of the industry

standard 16 pin narrow body SOIC, 16 pin ZIP (zig-zag in line package),

and 24 pin TSSOP.

UC5613

9-Line Low Capacitance SCSI Active Terminator

FEATURES

DESCRIPTION

BLOCK DIAGRAM

Circuit Design Patented

3/97

UDG-94003-1