LT3082

13

3082f

APPLICATIONS INFORMATION

Tables 3 through 5 list thermal resistance as a function

of copper areas in a fixed board size. All measurements

were taken in still air on a 4-layer FR-4 board with 1oz

solid internal planes and 2oz external trace planes with a

total finished board thickness of 1.6mm.

Table 3. DD Package, 8-Lead DFN

COPPER AREA

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)

TOPSIDE*

BACKSIDE

BOARD AREA

25°C/W

25°C/W

28°C/W

32°C/W

*Device is mounted on topside

Table 4. TS8 Package, 8-Lead SOT-23

COPPER AREA

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)

TOPSIDE*

BACKSIDE

BOARD AREA

54°C/W

54°C/W

57°C/W

63°C/W

*Device is mounted on topside

Table 5. ST Package, 3-Lead SOT-223

COPPER AREA

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)

TOPSIDE*

BACKSIDE

BOARD AREA

20°C/W

20°C/W

24°C/W

29°C/W

*Device is mounted on topside

For further information on thermal resistance and using thermal information,

refer to JEDEC standard JESD51, notably JESD51-12.

PCB layers, copper weight, board layout and thermal vias

affect the resultant thermal resistance. Please reference

JEDEC standard JESD51-7 for further information on high

thermal conductivity test boards. Achieving low thermal

resistance necessitates attention to detail and careful layout.

Demo circuit 1447A’s board layout using multiple inner

performance for the DFN package.

Calculating Junction Temperature

Example: Given an industrial factory application with an

input voltage of 15V ±10%, an output voltage of 12V ±5%,

an output current of 200mA and a maximum ambient

temperature of 50°C, what would be the maximum junc-

tion temperature for a DFN package?

The total circuit power equals:

The SET pin current is negligible and can be ignored.

Power dissipation under these conditions equals:

Junction temperature equals:

In this example, junction temperature is below the maxi-

mum rating, ensuring reliable operation.