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CY2037
Document Number: 38-07354 Rev. *E
Page 9 of 11
Switching Waveforms
Figure 2. Duty Cycle Timing (t1w, t1x, t1y, t1z)
Figure 3. Output Rise/Fall Time
Figure 4. Power Down Timing (synchronous and asynchronous modes)
Figure 5. Power Up Timing
t1A
t1B
OUTPUT
OUTPUT
t2
VDD
0V
t3
CLKOUT
VDD
t4
1/f
t5a
VIL
VIH
POWER
DOWN
0V
1/f
t5b
CLKOUT
T
(synchronous
[9])
(asynchronous
[10])
CLKOUT
VDD
t6
1/f
VDD – 10%
POWER
UP
0V
min. 30
μs
max. 30 ms
Notes
9. In synchronous mode the power down or output tri-state is not initiated until the next falling edge of the output clock.
10. In asynchronous mode the power down or output tri-state occurs within 25 ns regardless of position in the output clock cycle.
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