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CY2308
Document Number: 38-07146 Rev. *H
Page 9 of 15
Typical Duty Cycle[10] and IDD Trends
[11] for CY2308–1,2,3,4
Notes
10. Duty cycle is taken from typical chip measured at 1.4V.
11. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current.
(n = number of outputs; C = Capacitance load per output (F); V = Voltage Supply (V); f = frequency (Hz).
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3
3.1
3.23.3
3.43.5
3.6
VDD (V)
33 MHz
66 MHz
100 MHz
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
33 MHz
66 MHz
100 MHz
133 MHz
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20
40
60
80
100
120
140
Frequency (MHz)
-40C
0C
25C
70C
85C
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20
40
60
80
100
120
140
Frequency (MHz)
-40C
0C
25C
70C
85C
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
02
468
N umb er o f Lo ad ed O ut p ut s
33 M Hz
66 M Hz
100 M Hz
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
0
246
8
N umb er o f Lo ad ed O ut p ut s
33 M Hz
66 M Hz
100 M Hz
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