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LTC2634

2634f

OPERATION

The LTC2634 is a family of quad voltage output DACs in

16-lead QFN and 10-lead MSOP packages. Each DAC can

operate rail-to-rail using an external reference, or with its

full-scale voltage set by an integrated reference. Eighteen

combinations of accuracy (12-, 10- and 8-bit), power-on

reset value (zero-scale, mid-scale in internal reference

mode, or mid-scale in external reference mode), and full-

scale voltage (2.5V or 4.096V) are available. The LTC2634

is controlled using a 3-wire SPI/MICROWIRE compatible

interface.

Power-On Reset

The LTC2634-HZ/LTC2634-LZ clear the output to zero-scale

when power is ﬁrst applied, making system initialization

consistent and repeatable.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2634

contains circuitry to reduce the power-on glitch: the

analog output typically rises less than 5mV above zero-

scale during power on. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See “Power-On Reset Glitch” in the Typical Performance

Characteristics section.

The LTC2634-HMI/LTC2634-HMX/LTC2634-LMI/

LTC2634-LMX provide an alternative reset, setting the

output to mid-scale when power is ﬁrst applied. The

LTC2634-LMI and LTC2634-HMI power up in internal

reference mode, with the output set to a mid-scale volt-

age of 1.25V and 2.048V, respectively. The LTC2634-LMX

and LTC2634-HMX power up in external reference mode,

with the output set to mid-scale of the external reference.

Default reference mode selection is described in the Refer-

ence Modes section.

Power Supply Sequencing

The voltage at REF (Pin 10, QFN/Pin 7, MSOP) must be

kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see

Absolute Maximum Ratings). Particular care should be

taken to observe these limits during power supply turn-

on and turn-off sequences, when the voltage at VCC is in

transition.

Transfer Function

The digital-to-analog transfer function is:

OUT IDEAL

REF

REFLO

()

–

= ⎛

⎝⎜

⎞

⎠⎟ ()

where k is the decimal equivalent of the binary DAC

input code, N is the resolution, and VREF is either 2.5V

(LTC2634-LMI/LTC2634-LMX/LTC2634-LZ) or 4.096V

(LTC2634-HMI/LTC2634-HMX/LTC2634-HZ) when in

internal reference mode, and the voltage at REF when in

external reference mode. The resulting DAC output span

is 0V to VREF, as it is necessary to tie REFLO to GND.

Serial Interface

The CS/LD input is level-triggered. When this input is

taken low, it acts as a chip-select signal, enabling the SDI

and SCK buffers and the input shift register. Data (SDI

input) is transferred at the next 24 rising SCK edges.

The 4-bit command, C3-C0, is loaded ﬁrst; then the 4-bit

DAC address, A3-A0; and ﬁnally the 16-bit data word.

The data word comprises the 12-, 10- or 8-bit input code,

ordered MSB to LSB, followed by 4, 6 or 8 don’t-care

bits (LTC2634-12/LTC2634-10/LTC2634-8 respectively;

see Figure 2). Data can only be transferred to the device

when the CS/LD signal is low, beginning on the ﬁrst rising

edge of SCK. SCK may be high or low at the falling edge

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