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12/19/97

SPT7730

should be taken to ensure that the LSB is latched into an

external latch with the proper amount of set and hold time.

DATA OUTPUT CODING

The coding of the output is straight binary. (See table I.)

Table I - Data Output Coding

ANALOG INPUT

OUTPUT CODE D7 - DO

+FS - 1/2 LSB

1111

1 1 1 Ø

+1/2 FS

ØX X X

XXXX

+1/2 LSB

OOOO

OOOØ

OOOO

OOOO

Ø indicates the flickering bit between logic O and 1.

X indicates the flickering bit between logic 1 and O.

ANALOG INPUT AND REFERENCE SETTLING TRACK

AND HOLD TIMING

Figure 9 shows the timing relationship between the input

settling. The analog input is tracked from the twelfth clock

cycle of the previous conversion to the third clock cycle of the

current conversion. On the falling edge of the third clock

cycle, the analog input is held by the internal sample-and-

hold. After this sample, the analog input may vary without

affecting data conversion.

changed starting on the falling edge of the eleventh clock

cycle of the previous conversion and must be settled by the

falling edge of the third clock cycle of the current conversion.

(See figure 9.)

VOLTAGE REFERENCE AND ANALOG INPUT

The SPT7730 requires the use of a single external voltage

reference for driving the high side of the reference ladder.

side of the ladder is typically tied to AGND (0.0 V) but can be

For example,

The +Full Scale (+FS) of the analog input is expected to be 6%

Therefore,

For example,

Analog + FS = 3 V - 0.06 * [3 V- 0 V ] = 2.82 V, and

Analog - FS = 0 V + 0.04 * [3 V - 0 V] = 0.12 V.

GENERAL DESCRIPTION AND OPERATION

The SPT7730 is an 8-bit analog-to-digital converter that

uses a successive approximation architecture to perform

data conversion. Each conversion cycle is 12 clocks in

conversion begins on the next rising edge of the input clock.

When the conversion cycle begins, the data output pin is

forced low until valid data output begins.

The first two clock cycles are used to perform internal offset

calibrations and to track the analog input. The analog input

is then sampled using an internal track-and-hold amplifier on

the falling edge of the third clock cycle. On clock cycles 4

through 12, an 8-bit successive approximation conversion is

performed, and the data is output starting with the MSB.

Serial data output begins with output of the MSB. See the

Data Output Timing section for details. Each bit of the data

conversion is sequentially determined and placed on the

data output pin at the clock rate. This process continues until

the LSB has been determined and output. At this point, if the

impedance state, and the converter will go into an idle state

Shot Mode. See Modes of Operation for details.

conversion cycle (free run mode) or is brought low prior to the

trailing edge of the twelfth clock cycle (synchronous mode),

the data output pin goes low and stays low until valid data

output begins. Because the chip has either remained se-

lected in the free run mode or has been immediately selected

again in the synchronous mode, the next conversion cycle

begins immediately after the twelfth clock cycle of the previ-

ous conversion. See Modes of Operation for details.

TYPICAL INTERFACE CIRCUIT

CLOCK INPUT

The SPT7730 requires a 50%

±10 % duty cycle clock running

at 12 times the desired sample rate. The clock may be

stopped in between conversion cycles without degradation

of operation (single shot type of operation), however, the

clock should remain running during a conversion cycle.

POWER SUPPLY

The SPT7730 requires only a single supply and operates

capacitor be placed as close as possible to the supply pin.

DATA OUTPUT SET UP AND HOLD TIMING

As figure 8 shows, all of the data output bits (except the LSB)

remains valid for a duration equivalent to one clock period

and delayed by 8 ns after the falling edge of clock. Because

the data converter enters into a next conversion ready state

at the leading edge of clock 12, the LSB bit is valid for a

duration equivalent to only the clock pulse width low

and delayed by 8 ns after the falling edge of clock. Care

from 3.0 V to 5.0 V. CADEKA recommends that a 0.01

µF chip