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TMC22X5YA Datasheet(PDF) 32 Page - Cadeka Microcircuits LLC. |
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TMC22X5YA Datasheet(HTML) 32 Page - Cadeka Microcircuits LLC. |
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32 / 84 page  TMC22x5yA PRODUCT SPECIFICATION 32 REV. 1.0.0 2/4/03 Control Register Definitions (continued) Buffered register set 1 (2D) Active when BUFFER pin set HIGH. 76543210 Reserved YOFF18 SG19 SG18 Reg Bit Name Description 2D 7-3 Reserved Reserved, set to zero. 2D 2 YOFF18 Y offset, msb. msb of YOFF 2D 1-0 SG19,8 Msync gain, 2 msbs. Top 2 bits of mixed sync scalar msb = 2 Buffered register set 1 (2E) Active when BUFFER pin set HIGH. 76543210 SYSPH16 SYSPH15 SYSPH14 SYSPH13 SYSPH12 SYSPH11 SYSPH10 VAXISO Reg Bit Name Description 2E 7-1 SYSPH16-0 7 lsbs of phase offset. Bottom 7 bits of the 15 bit system phase offset 2E 0 VAXIS1 V axis flip. Flips the sign of the V axis when HIGH. Buffered register set 1 (2F) Active when BUFFER pin set HIGH. 76543210 SYSPH114 SYSPH113 SYSPH112 SYSPH111 SYSPH110 SYSPH19 SYSPH18 SYSPH17 Reg Bit Name Description 2F 7-0 SYSPH114-7 8 msbs of phase offset. Top 8 bits of 15 bit system phase offset. |
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