TMC2490AR2C datasheet(3/36 Pages) CADEKA

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PRODUCT SPECIFICATION

TMC2490A

Pin Assignments

Pin Descriptions

Pin Name

Pin Number

Value

Pin Function Description

Clock

PXCK

TTL

Pixel Clock Input. This 27.0 MHz clock is internally divided by 2

to generate the internal pixel clock. PXCK drives the entire

TMC2490A, except the asynchronous microprocessor interface.

All internal registers are strobed on the rising edge of PXCK.

Data Input Port

PD7-0

38–44, 3

TTL

Pixel Data Inputs. Video data enters the TMC2490A on

PD7-0 (Figure 1).

Microprocessor Interface

D7-0

9–12, 14–17

TTL

Data I/O, General Purpose I/O, Chroma Input Port. When SER

is HIGH, all control parameters are loaded into and read back

over this 8-bit port. When SER = LOW, D0 can serve as a

composite sync output, D1 outputs a burst flag during the back

porch, D2-5 are General Purpose Outputs, and D6-7 are General

Purpose Inputs.

RESET

TTL

Master Reset Input. Bringing RESET LOW forces the internal

state machines to their starting states and disables all outputs.

SA1

TTL

Serial/Parallel Port Select. When SER is LOW, SA1 in

conjunction with SA0 selects one of four addresses for the

TMC2490A.

SA0, ADR

TTL

Serial/Parallel Port Select. When SER is LOW, SA0 in

conjunction with SA1 selects one-of-four addresses for the

TMC2490A. When SER is HIGH, this control governs whether the

parallel microprocessor interface selects a table address or

reads/writes table contents.

65-2490(1)A-02

SCL/CS

SER

GND

PD6

PD7

VDD

GND

CHROMA

VDDA

CBYP

LUMA

GND

COMPOSITE

GND

TMC2490A

TMC2490AR2C Datasheet(PDF) 3 Page - Cadeka Microcircuits LLC.

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