TMC22091KHC datasheet(8/60 Pages) CADEKA

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TMC22091/TMC22191

PRODUCT SPECIFICATION

OL4-0

29, 48-51 97, 22-25

TTL

Overlay Data Inputs (TMC22191 only). 30 of the 256

locations of the CLUT may be reserved for overlay operation.

These CLUT locations are directly accessed by five input pins,

OL4-0. OL4-0 are entered into the TMC22191 on a pixel-by-

pixel basis and select which of the 30 overlay colors is to be

encoded. When all five OL4-0 inputs are LOW, no overlay

occurs.

BYPASS

TTL

CLUT Bypass Control (TMC22191 only). When BYPASS is

HIGH, the CLUT is in the pixel data path within the TMC22191.

When BYPASS is LOW, pixel data bypasses the CLUT.

BYPASS is active only for certain modes of the Layering

Control Register (LCR) when the Format Control Register bit 6

is HIGH.

Genlock Interface

GHSYNC

CMOS

Genlock Horizontal Sync. In Genlock mode, the TMC22x91

will start a new horizontal line (blank-to-sync-edge transition)

with each falling edge of GHSYNC. In non-genlock modes, the

TMC22x91 ignores GHSYNC. The internal pixel clock, PCK, is

aligned with the falling edge of VHSYNC or GHSYNC (Genlock

mode).

GVSYNC

CMOS

Genlock Vertical Sync. In Genlock mode, the TMC22x91 will

start a new vertical sync sequence at line 1 field 1 whenever

GVSYNC and GHSYNC are coincident such that they are

clocked into the TMC22x91 on the same rising edge of PXCK.

If GVSYNC falls at any other time, the TMC22x91 will assume

that this marks the start of field 2, and will ignore it (in odd-field

sync mode) or (in all-field sync mode) respond by generating a

single vertical sync pulse, followed by 2 (PAL) or 2.5 (NTSC)

lines of vertical sync, keyed to the next falling edge on

GHSYNC. See Interface Control Register bit 0 for odd-field and

all-field operation.

CVBS7-0

44-47, 84,

1-3

18-21,

65-68

TTL

Composite Video Inputs. The encoder receives digitized

video, subcarrier phase, and subcarrier frequency over this 8-

bit bus at the PCK rate. This data may be provided by the

companion TMC22071 Genlocking Video Digitizer. In Genlock

mode, the TMC22x91 expects subcarrier phase and frequency

data during each line’s horizontal sync interval, as well as video

data when keying is engaged, transferred at the PCK rate.

Microprocessor Interface

D7-0

14-21

82-89

TTL

Data I/O Port. All control parameters are loaded into and read

back over this 8-bit port. For digital testing, the five lower bits

can also serve as a two-cycle 10-bit data output port. For D/A

converter testing, it can be used as a 10-bit two-cycle input

port, facilitating, for example, ramp-based D/A converter

linearity tests.

A1-0

8-9

74-75

TTL

µProc Port Controls. As in a RAMDAC, this control governs

whether the microprocessor interface selects a table address

or reads/writes table contents. It also governs setting and

verification of the TMC22x91’s internal operating modes, also

over port D7-0.

Pin Descriptions (continued)

Pin Name

Pin Number

Value

Pin Function Description

84-Lead

PLCC

100-Lead

MQFP

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