The circuit below is a guideline for interconnecting PCA’s EPA1829B with a typical 10 Base-T PHY chip over UTP cable.

Further details of system design, such as chip pin-out, etc. can be obtained from the specific chip manufacturer.

Typical insertion loss of the isolation transformer/filter is 0.7dB. This parameter covers the entire spectrum of the encoded

signals in 10 Base-T protocols. However, the predistortion resistor network introduces some loss which has to be taken

into account in determining how well your design meets the Standard Template requirements. Additionally, the following

need to be considered while selecting resistor values :

a. The filter needs 100

Ω termination, thus the Thevenin’s equivalent resistance seen by the filter looking into the transmit

outputs from the chip must be equal to a value close to 100

Ω. The typical driver output impedance is 5Ω. Thus

choose R1 and R2 values that are lowered by 5

Ω on each leg. Following these guidelines will guarantee that the

return loss specifications are satisfied at all extremes of cable impedance (i.e. 85

Ω to 115Ω) while the module is

installed in your system.

b. That the template requirements are satisfied under the worst case Vcc (i.e. 4.5V), will impose a further constraint on

resistor selection, in that they ought to be the minimum derived from the calculations. Add R3 for more flexibility in

setting voltage levels at the outputs.

Note that some systems have auto polarity detection and some do not. If not, be certain to follow the proper polarity.

It is recommended that system designers ground the chip side center taps via a low voltage capacitor. Taking the cable

side center taps to chassis via capacitors, is not recommended, as this will add cost without containing EMI. This may

worsen EMI, specifically if the primary “common mode termination” is pulled to ground as shown.

The pulldown resistors used around the RJ45 connector have been known to suppress unwanted radiation that unused

wires pick up from the immediate environment. Their placement and use are to be considered carefully before a design is

finalized.

It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit

the plane off at least 0.08 inches away from the chip side pins of EPA1829B. There need not be any ground plane beyond

this point.

For best results, PCB designer should design the outgoing traces preferably to be 50

Ω, balanced and well coupled to

achieve minimum radiation from these traces.

CSA1829Bb

Rev. C1

5/2/97

10 Base-T Interface Module with

Enhanced Common Mode Attenuation

Typical Application Circuit for UTP with external Resistor Network

E L E C T R O N I C S I N C .

EPA1829B

10 Base-T

PHY

RJ45*

3

6

2

1

TX+

TXd+

RX+

RX-

EPA1829B

TX+

TX-

RX-

1

2

3

R1

R1

R2

R2

TX-

TXd-

Notes : * Pin-outs shown are for multiport, DCE configurations : e.g. Hubs, Repeaters

For NIC’s, swap pins 3-6 with pins 1-2.

Chassis

Ground

8

7

45

16

14

11

6

RX+

9

8

7

TEL: (818) 892-0761

FAX: (818) 894-5791

http://www.pca.com

PCA ELECTRONICS, INC.

16799 SCHOENBORN ST.

NORTH HILLS, CA 91343