CSE6199Sb

Rev. -

6/5/97

10 Base-T Interface Module

E L E C T R O N I C S I N C .

EPE6199S

TEL: (818) 892-0761

FAX: (818) 894-5791

http://www.pca.com

PCA ELECTRONICS, INC.

16799 SCHOENBORN ST.

NORTH HILLS, CA 91343

The circuit below is a guideline for interconnecting PCA’s EPE6199S with LXT905 10 Base-T PHY chip over UTP cable.

Further details of system design, such as chip pin-out, etc. can be obtained from the specific chip manufacturer.

Typical insertion loss of the isolation transformer is 0.7dB. This parameter covers the entire spectrum of the encoded signals

in 10 Base-T protocols. However, the predistortion resistor network introduces some loss which has to be taken into account

in determining how well your design meets the Standard Template requirements. Additionally, the following need to be

considered while selecting resistor values :

a. Each channel needs 100

Ω termination, thus the Thevenin’s equivalent resistance seen by a channel looking into the

transmit outputs from the chip must be equal to a value close to 100

Ω. The LXT 905 driver output impedances are very low.

. Thus only 11.8

Ω on TPON & TPOP are enough to provide a balanced 25 Ω termination given that turns ratio is 1:2.

Following these guidelines will guarantee that the return loss specifications are satisfied at all extremes of cable impedance

(i.e. 85

Ω to 115Ω) while the module is installed in your system. The receiver channel termination is rather straight forward:

two 50

Ω loads provide the balanced termination to the cable.

b. That the template requirements are satisfied under the worst case Vcc (i.e. 4.5V), will impose a further constraint on

resistor selection, in that they ought to be the minimum derived from the calculations. Users can allow for pads on their PCB

for a shunting resistor across pins 6 and 8 of EPE6199S for more flexibility in setting voltage levels at the outputs.

Note that some systems have auto polarity detection and some do not. If not, be certain to follow the proper polarity.

The pulldown resistors used around the RJ45 connector have been known to suppress unwanted radiation that unused wires

pick up from the immediate environment. Their placement and use are to be considered carefully before a design is finalized.

It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit the

plane off at least 0.08 inches away from the chip side pins of EPE6199S. There need not be any ground plane beyond this

point.

For best results, PCB designer should design the outgoing traces preferably to be 50

Ω, balanced and well coupled to achieve

minimum radiation from these traces.

Typical Application Circuit for UTP for one port only.

LXT905

PHY

RJ45*

3

6

2

1

TPIN

TPIP

TPON

TPOP

EPE6199S

TX+

TX-

RX+

RX-

9

8

Notes : * Pin-outs shown are for Hubs and Repeaters.

Chassis

Ground

8

7

45

39

38

2

3

34

33

0.1

µF

X7R

High voltage cap, if used

2KV recommended

0.1

µF

X7R

1

10