DS2756: High-Accuracy Battery Fuel Gauge with Programmable Suspend Mode

EEC

—EEPROM Copy Flag. A 1 in this read-only bit indicates that a Copy Data command is in progress. While this

bit is high, writes to EEPROM addresses are ignored. A 0 in this bit indicates that data can be written to unlocked

EEPROM blocks.

LOCK

—EEPROM Lock Enable. When this bit is 0, the Lock command is ignored. Writing a 1 to this bit enables the

Lock command. After the Lock command is executed, the LOCK bit is reset to 0. The factory default is 0.

BL2—

EEPROM Block 2 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 2 (addresses 60h to 7Fh)

is locked (read-only), while a 0 indicates block 1 is unlocked (read/write).

BL1—

EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 1 (addresses 40h to 5Fh)

is locked (read-only), while a 0 indicates block 1 is unlocked (read/write).

BL0—

EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 0 (addresses 20h to 3Fh)

is locked (read-only), while a 0 indicates block 0 is unlocked (read/write).

X

—Reserved Bits.

SPECIAL FEATURE REGISTER

The format of the Special Feature Register is shown in Figure 17. The function of each bit is described in detail in

the following paragraphs.

Figure 17. Special Feature Register Format

Address 08h

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

POR

PIO

X

X

X

IE

X

SNAP

POR—

POR Indicator bit. This bit is set to a 1 when the DS2756 experiences a power-on-reset (POR) event. To

use the POR bit to detect a power-on-reset, the POR bit must be set to a 0 by the host system upon power-up and

after each subsequent occurrence of a POR. This bit is read/write to 0.

PIO—

PIO Pin Sense and Control. See the Programmable I/O section for details on this read/write bit.

IE—

Interrupt Enable. A value of 1 in this bit location enables Alarm Comparator interrupt signaling to the host

system. When IE is 0, Alarm Comparator interrupt signaling is disabled and the alarm comparator registers are

available as SRAM and have no effect on device operation. IE bit is read/write to 1. IE is cleared to 0 by a 1-Wire

RESET on DQ.

SNAP—

Snapshot Control. This bit is set to a 1 immediately after the DS2756 executes a Snapshot conversion

pair. SNAP = 1 indicates that the Current and Voltage registers contain Snapshot results. While SNAP = 1, the

Snapshot results persist in the Current and Voltage registers until the SNAP bit is written to a 0 by the host system.

This bit is read/write to 0.

X

—Reserved Bits.

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