DS3105_09 datasheet(21/120 Pages) MAXIM

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_____________________________________________________________________________________________ DS3105

19-4628; Rev 3; 5/09

21 of 120

Table 7-3. Default Input Clock Priorities

INPUT CLOCK

T0 DPLL

DEFAULT

PRIORITY

IC3

IC4

IC5

0 (off)

IC6

0 (off)

IC9

7.6.2 Automatic Selection Algorithm

The real-time valid/invalid state of each input clock is maintained in the VALSR1 and VALSR2 registers. The

selected reference can be marked invalid for phase lock, frequency, or activity. Other input clocks can be

invalidated for frequency or activity.

The reference selection algorithm for the T0 DPLL chooses the highest priority valid input clock to be the selected

reference. To select the proper input clock based on these criteria, the selection algorithm maintains a priority table

of valid inputs. The top three entries in this table and the selected reference are displayed in the PTAB1 and

PTAB2 registers. When T4T0 = 0 in the MCR11 register, these registers indicate the highest priority input clocks

for the T0 DPLL. When T4T0 = 1, they have no meaning.

If two or more input clocks are given the same priority number, those inputs are prioritized among themselves using

a fixed circular list. If one equal-priority clock is the selected reference but becomes invalid, the next equal-priority

clock in the list becomes the selected reference. If an equal-priority clock that is not the selected reference

becomes invalid, it is simply skipped over in the circular list. The selection among equal-priority inputs is inherently

nonrevertive, and revertive switching mode (see next paragraph) has no effect in the case where multiple equal-

priority inputs have the highest priority.

An important input to the selection algorithm for the T0 DPLL is the REVERT bit in the MCR3 register. In revertive

mode (REVERT = 1), if an input clock with a higher priority than the selected reference becomes valid, the higher

priority reference immediately becomes the selected reference. In nonrevertive mode (REVERT = 0), the higher

priority reference does not immediately become the selected reference but does become the highest priority

reference in the priority table (REF1 field in the PTAB1 register). (The selection algorithm always switches to the

highest priority valid input when the selected reference goes invalid, regardless of the state of the REVERT bit.) For

many applications, nonrevertive mode is preferred for the T0 DPLL because it minimizes disturbances on the

output clocks due to reference switching.

In nonrevertive mode, planned switchover to a newly valid higher priority input clock can be done manually under

software control. The validation of the new higher priority clock sets the corresponding status bit in the MSR1 or

MSR2 register, which can drive an interrupt request on the INTREQ pin if needed. System software can then

respond to this change of state by briefly enabling revertive mode (toggling REVERT high then back low) to drive

the switchover to the higher priority clock.

7.6.3 Forced Selection

The T0FORCE field in the MCR2 register and the T4FORCE field in the MCR4 register provide a way to force a

specified input clock to be the selected reference for the T0 and T4 DPLLs, respectively. In both T0FORCE and

T4FORCE, values of 0 and 15 specify normal operation with automatic reference selection. Values from 3 to 6 and

9 specify the input clock to be the forced selection; other values will cause no input to be selected. Internally,

forcing is accomplished by giving the specified clock the highest priority (as specified in PTAB1:REF1). In revertive

mode (MCR3:REVERT = 1) the forced clock automatically becomes the selected reference (as specified in

PTAB1:SELREF) as well. In nonrevertive mode (T0 DPLL only) the forced clock only becomes the selected

reference when the existing selected reference is invalidated or made unavailable for selection. In both revertive

and nonrevertive modes when an input is forced to be the highest priority, the normal highest priority input (when

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