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CS5560 Datasheet(PDF) 28 Page - Cirrus Logic

Part # CS5560
Description  짹2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ?誇 ADC
PDF  32 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5560 Datasheet(HTML) 28 Page - Cirrus Logic

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CS5560
28
DS713PP2
5/4/09
4. PIN DESCRIPTIONS
CS – Chip Select, Pin 1
The Chip Select pin allows an external device to access the serial port. If SMODE = VL (SSC
Mode) and CS is held high, the SDO output and the SCLK output will be held in a
high-impedance output state.
TST – Factory Test, Pin 2
For factory use only. Connect to VLR.
SMODE – Serial Mode Select, Pin 3
The serial interface mode pin (SMODE) dictates whether the serial port behaves as a master or
slave interface. If SMODE is tied high (to VL), the port will operate in the Synchronous
Self-Clocking (SSC) mode. In SSC mode, the port acts as a master in which the converter out-
puts both the SDO and SCLK signals. If SMODE is tied low (to VLR), the port will operate in the
Synchronous External Clocking (SEC) mode. In SEC mode, the port acts as a slave in which
the external logic or microcontroller generates the SCLK used to output the conversion data
word from the SDO pin.
AIN+, AIN- – Differential Analog Input, Pins 4, 5
AIN+ and AIN- are differential inputs for the converter.
V1- – Negative Power 1, Pin 6
The V1- and V2- pins provide a negative supply voltage to the core circuitry of the chip. These
two pins should be decoupled as shown in the application block diagrams. V1- and V2- should
be supplied from the same source voltage. For single-supply operation, these two voltages are
nominally 0 V (Ground). For dual-supply operation, they are nominally -2.5 V.
V1+ – Positive Power 1, Pin 7
The V1+ and V2+ pins provide a positive supply voltage to the core circuitry of the chip. These
two pins should be decoupled as shown in the application block diagrams. V1+ and V2+ should
be supplied from the same source voltage. For single-supply operation, these two voltages are
nominally +5 V. For dual-supply operation, they are nominally +2.5 V.
BUFEN – Buffer Enable, Pin 8
Buffers on input pins AIN+ and AIN- are enabled if BUFEN is connected to V1+ and disabled if
connected to V1-.
VREF+, VREF- – Voltage Reference Input, Pins 9, 10
A differential voltage reference input on these pins functions as the voltage reference for the
converter. The voltage between these pins can range between 2.4 volts and 4.2 volts, with
4.096 volts being the nominal reference voltage value.
SLEEP
12
Sleep Mode Select
BP/UP
11
Bipolar/Unipolar Select
VREF-
10
Voltage Reference Input
VREF+
9
Voltage Reference Input
BUFEN
8
Buffer Enable
V1+
7
Positive Power 1
V1-
6
Negative Power 1
AIN-
5
Differential Analog Input
AIN+
4
Differential Analog Input
3
2
CS
1
Chip Select
RST
13
Reset
VLR2
14
Logic Interface Return
CONV
15
Convert
DCR
16
Digital Core Regulator
V2+
17
Positive Voltage 2
V2-
18
Negative Voltage 2
MCLK
19
Master Clock
VLR
20
Logic Interface Return
VL
21
Logic Interface Power
SDO
22
Serial Data Output
SCLK
23
Serial Clock Input/Output
RDY
24
Ready
TST
Factory Test
SMODE
Serial Mode Select



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