ADC

ADC

ADC

ADC

ADC

AS1419

AS1419A

AS1419 & AS1419A

Rev. 1.5 08/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

13

Austin Semiconductor, Inc.

BOARD LAYOUT AND GROUNDING

Wire wrap boards are not recommended for high

resolution or high speed A/D converters. To obtain the best

performance from theAS1419, a printed circuit board with ground

plane is required. Layout should ensure that digital and analog

signal lines are separated as much as possible. Particular care

should be taken not to run any digital track alongside an

analog signal track or underneath the ADC.The analog input

should be screened by AGND.

An analog ground plane separate from the logic system

ground should be established under and around the ADC. Pin

5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all other

analog grounds should be connected to this single analog

ground point. The REFCOMP bypass capacitor and the DV

DD

bypass capacitor should also be connected to this analog

ground plane. No other digital grounds should be connected

to this analog ground plane. Low impedance analog and digital

power supply common returns are essential to low noise

operation of the ADC and the foil width for these tracks should

be as wide as possible. In applications where the ADC data

outputs and control signals are connected to a continuously

active microprocessor bus, it is possible to get errors in the

conversion results. These errors are due to feedthrough from

the microprocessor to the successive approximation

comparator. The problem can be eliminated by forcing the

microprocessor into a WAIT state during conversion or by

using three-state buffers to isolate the ADC data bus. The traces

connecting the pins and bypass capacitors must be kept short

and should be made as wide as possible.

The AS1419 has differential inputs to minimize noise

coupling. Common mode noise on the +A

IN

and –A

IN

leads will

be rejected by the input CMRR. The –A

IN

input can be used as

a ground sense for the +A

IN

input; the AS1419 will hold and

convert the difference voltage between +A

IN

and –A

IN

. The

leads to +A

IN

(Pin 1) and –A

IN

(Pin 2) should be kept as short as

possible. In applications where this is not possible, the +A

IN

and –A

IN

traces should be run side by side to equalize

coupling.

SUPPLY BYPASSING

High quality, low series resistance ceramic, 10µF bypass

capacitors should be used at the V

DD

and REFCOMP pins.

Surface mount ceramic capacitors provide excellent bypassing

in a small board space. Alternatively, 10µF tantalum capacitors

in parallel with 0.1µF ceramic capacitors can be used. Bypass

capacitors must be located as close to the pins as

possible.

The traces connecting the pins and the bypass capacitors must

be kept short and should be made as wide as possible.

DIGITAL INTERFACE

The A/D converter is designed to interface with

microprocessors as a memory mapped device. The CS\ and RD\

control inputs are common to all peripheral memory interfacing.

A separate CONVST\ is used to initiate a conversion.

Internal Clock

The A/D converter has an internal clock that eliminates the

need of synchronization between the external clock and the CS\

and RD\ signals found in other ADCs. The internal clock is

factory trimmed to achieve a typical conversion time of 0.95

μs

and a maximum conversion time over the full operating

temperature range of 1.15

μs. No external adjustments are

required. The guaranteed maximum acquisition time is 300ns. In

addition, a throughput time of 1.25

μs and a minimum sampling

rate of 800ksps are guaranteed.

FIGURE 12: Power Supply Grounding Practice