AD9573

Rev. 0 | Page 2 of 12

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications....................................................................................... 1

 

General Description ......................................................................... 1

 

Functional Block Diagram .............................................................. 1

 

Revision History ............................................................................... 2

 

Specifications..................................................................................... 3

 

PLL Characteristics ...................................................................... 3

 

Clock Output Jitter ....................................................................... 3

 

Clock Outputs ............................................................................... 3

 

Timing Characteristics ................................................................ 4

 

Control Pins .................................................................................. 4

 

Power.............................................................................................. 4

 

Crystal Oscillator.......................................................................... 4

 

Timing Diagrams.......................................................................... 4

 

Absolute Maximum Ratings............................................................ 5

 

Thermal Resistance ...................................................................... 5

 

ESD Caution...................................................................................5

 

Pin Configuration and Function Descriptions..............................6

 

Typical Performance Characteristics ..............................................7

 

Terminology .......................................................................................8

 

Theory of Operation .........................................................................9

 

Outputs ...........................................................................................9

 

Phase Frequency Detector (PFD) and Charge Pump ..........9

 

Power Supply..................................................................................9

 

LVDS Clock Distribution .......................................................... 10

 

CMOS Clock Distribution ........................................................ 10

 

Power and Grounding Considerations and Power Supply

Rejection...................................................................................... 10

 

Outline Dimensions ....................................................................... 11

 

Ordering Guide .......................................................................... 11

 

REVISION HISTORY

7/09—Revision 0: Initial Version