SC3333

TIMIING CHARACTERISTICS1,2

Parameter

Test Condition

Test Data

Units

t1

3

F1 and F2 Pulse-width

275

ms

t2

F1 and F2 Pulse Period.

TBD

sec

t3

Time Between F1 Falling Edge and F2 Falling Edge

1/2 t2

sec

t4

3

CF Pulse-width

90

ms

t5

CF Pulse Period.

TBD

sec

t6

Minimum Time Between F1 and F2 Pulse

CLKIN/4

sec

NOTE: 1. Sample tested during initial release and after any redesign or process change that may after this

parameter.

2. See the following figure.

3. The pulse-widths of F1, F2 and CF are not fixed for higher output frequencies.

Timing Diagram for Frequency outputs

Timing Diagram for Frequency Outputs shows a timing diagram for the various frequency outputs of the

SC3333. The low frequency outputs, F1 and F2 can drive electromechanical counters and two phase stepper

motors directly. As the figure show, the F1 and F2 outputs provide two alternating low going pulses. The pulse

width (t1) is set at 275ms and the time between the falling edges of F1 and F2 (t3) is approximately half the

period of F1 (t2). If however the period of F1 and F2 falls below 550 ms (1.81Hz) the pulse width of F1 and F2 is

set to half of their period. The frequency of F1 and F2 corresponds to the input voltages, and F=

（13.6*V1*V2*G）/ VREF

table I , V1 and V2 are the rms value of the two inputs, VREF is the voltage of reference, whose value is 2.5+0.2v

when the internal bandgap reference of SC3333 is valid.

The high frequency output, CF is intended for calibration and supplies instantaneous real power. CF produces

period of CF (t5) falls below 180ms, the CF pulse-width is set to half the period.

APPENDIX

Table I. gain selection for channel 1

SET

Gain

Maximum Differential Signal

0

1

±470mV

1

16

±30mV

HANGZHOU SILAN MICROELECTRONICS CO.,LTD

REV:1.1

2008.04.29

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