XR16M698 datasheet(9/58 Pages) EXAR

9 / 58 page

XR16M698

REV. 1.0.0

1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO

2.5

Crystal Oscillator

The 698 includes an on-chip oscillator. The crystal oscillator provides the system clock to the Baud Rate

Generators (BRG) in each of the 8 UARTs, the 16-bit general purpose timer/counter and internal logics. XTAL1

is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For programming

details, see “Section 2.6, Programmable Baud Rate Generator with Fractional Divisor” on page 9.

The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,

fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency

tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 3). Alternatively, an external

clock can be connected to the XTAL1 pin to clock the internal 8 baud rate generators for standard or custom

rates. The typical oscillator connections are shown in Figure 3. For further reading on oscillator circuit please

see application note DAN108 on EXAR’s web site.

FIGURE 3. TYPICAL OSCILLATOR CONNECTIONS

22-47pF

24 MHz

XTAL1

XTAL2

R=300K to 400K

2.6

Programmable Baud Rate Generator with Fractional Divisor

Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The

prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide

the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further

divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to

obtain a 16X or 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter

for data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to

the value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be

programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part

of the divisor and the DLD register provides the fractional part of the dvisior. Only the four lower bits of the DLD

are implemented and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting

1111). Programming the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for

selecting the operating data rate. Table 5 shows the standard data rates available with a 24MHz crystal or

external clock at 16X clock rate. If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times

less than that shown in Table 5. At 8X sampling rate, these data rates would double. Also, when using 8X

sampling mode, please note that the bit-time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is

an odd number. At 4X sampling rate, these data rates would quadruple. When using a non-standard data rate

crystal or external clock, the divisor value can be calculated with the following equation(s):

XR16M698 Datasheet(PDF) 9 Page - Exar Corporation