STM32F103CBU6TR datasheet(86/92 Pages) STMICROELECTRONICS

86 / 92 page

Revision history

STM32F103x8, STM32F103xB

86/92

Doc ID 13587 Rev 11

Revision history

Table 58.

Document revision history

Date

Revision

Changes

01-jun-2007

Initial release.

20-Jul-2007

Flash memory size modified in Note 8, Note 5, Note 7, Note 9 and

BGA100 pins added to Table 5: Medium-density STM32F103xx pin

definitions. Figure 3: STM32F103xx performance line LFBGA100

ballout added.

THSE changed to TLSE in Figure 21: Low-speed external clock source

AC timing diagram. VBAT ranged modified in Power supply schemes.

tSU(LSE) changed to tSU(HSE) in Table 22: HSE 4-16 MHz oscillator

characteristics. IDD(HSI) max value added to Table 24: HSI oscillator

characteristics.

Sample size modified and machine model removed in Electrostatic

discharge (ESD).

Number of parts modified and standard reference updated in Static

latch-up. 25 °C and 85 °C conditions removed and class name modified

in Table 33: Electrical sensitivities. RPU and RPD min and max values

added to Table 34: I/O static characteristics. RPU min and max values

added to Table 37: NRST pin characteristics.

Figure 26: I2C bus AC waveforms and measurement circuit and

Figure 25: Recommended NRST pin protection corrected.

Notes removed below Table 9, Table 37, Table 43.

IDD typical values changed in Table 11: Maximum current consumption

in Run and Sleep modes. Table 38: TIMx characteristics modified.

tSTAB, VREF+ value, tlat and fTRIG added to Table 45: ADC

characteristics.

In Table 29: Flash memory endurance and data retention, typical

endurance and data retention for TA = 85 °C added, data retention for

TA = 25 °C removed.

VBG changed to VREFINT in Table 12: Embedded internal reference

voltage. Document title changed. Controller area network (CAN)

section modified.

Figure 12: Power supply scheme modified.

Features on page 1 list optimized. Small text changes.

STM32F103CBU6TR Datasheet(PDF) 86 Page - STMicroelectronics

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