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MB90F455 Datasheet(PDF) 49 Page - fujitsu semiconductor |
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MB90F455 Datasheet(HTML) 49 Page - fujitsu semiconductor |
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49 / 80 page  MB90455 Series DS07-13728-5E 49 • UART block diagram SIN1 SCK1 SOT1 MD1 MD0 CS2 CS1 SCKE SOE TDRE BDS PEN P SBL CL A/D REC RXE CS0 TXE RIE TIE PE ORE FRE RDRF RST MD DIV2 DIV1 DIV0 Control bus Special-purpose baud-rate generator 16-bit reload timer Clock selector Pin Reception clock Reception control circuit Transmission control circuit Start bit detection circuit Transmission start circuit Transmission bit counter Transmission parity counter Transmission clock Reception interrupt request output Transmission interrupt request output Reception bit counter Reception parity counter Pin Pin Shift register for reception Serial input data register 1 Shift register for transmission Serial output data register 1 Start transmission Recep- tion com- pleted Reception error occurrence signal for EI2OS (to CPU) Reception status decision circuit Internal data bus Communi- cation prescaler control register Serial mode register 1 Serial control register 1 Serial status register 1 |
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