MCP3550 datasheet(13/36 Pages) MICROCHIP

13 / 36 page

DS21950E-page 13

MCP3550/1/3

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

3.1

Voltage Reference (VREF)

The MCP3550/1/3 devices accept single-ended

reference voltages from 0.1V to VDD. Since the

converter output noise is dominated by thermal noise,

which is independent of the reference voltage, the

output noise is not significantly improved by

diminishing the reference voltage at the VREF input pin.

A reduced voltage reference will significantly improve

the INL performance (see Figure 2-4); the INL max

error is proportional to VREF2.

3.2

Analog Inputs (VIN+, VIN-)

The MCP3550/1/3 devices accept a fully differential

analog input voltage to be connected on the VIN+ and

VIN- input pins. The differential voltage that is

converted is defined by VIN = VIN+ – VIN-. The

differential voltage range specified for ensured

accuracy is from -VREF to +VREF. However, the

converter will still output valid and usable codes with

the inputs overranged by up to 12% (see Section 5.0

“Serial Interface”) at room temperature. This

overrange is clearly specified by two overload bits in

the output code.

The absolute voltage range on these input pins extends

from VSS – 0.3V to VDD + 0.3V. Any voltage above or

below this range will create leakage currents through

the Electrostatic Discharge (ESD) diodes. This current

will increase exponentially, degrading the accuracy and

noise performance of the device. The common mode of

the analog inputs should be chosen such that both the

differential analog input range and the absolute voltage

range on each pin are within the specified operating

range

defined

Section 1.0

“Electrical

Characteristics”.

3.3

Supply Voltage (VDD, VSS)

VDD is the power supply pin for the analog and digital

circuitry within the MCP3550/1/3. This pin requires an

appropriate bypass capacitor of 0.1 µF. The voltage on

this pin should be maintained in the 2.7V to 5.5V range

for specified operation. VSS is the ground pin and the

current return path for both analog and digital circuitry

of the MCP3550/1/3. If an analog ground plane is

available, it is recommended that this device be tied to

the analog ground plane of the Printed Circuit Board

(PCB).

3.4

Serial Clock (SCK)

SCK synchronizes data communication with the

device. The device operates in both SPI mode 1,1 and

SPI mode 0,0. Data is shifted out of the device on the

falling edge of SCK. Data is latched in on the rising

edge of SCK. During CS high times, the SCK pin can

idle either high or low.

3.5

Data Output (SDO/RDY)

SDO/RDY is the output data pin for the device. Once a

conversion is complete, this pin will go active-low,

acting as a ready flag. Subsequent falling clock edges

will then place the 24-bit data word (two overflow bits

and 22 bits of data, see Section 5.0 “Serial

Interface”) on the SPI bus through the SDO pin. Data

is clocked out on the falling edge of SCK.

MCP3550/1/3

Symbol

I/O/P

Description

MSOP, SOIC

1VREF

Reference Voltage Analog Input Pin

2VIN+

Non-inverting Analog Input Pin

3VIN-

Inverting Analog Input Pin

4VSS

Ground Pin

SCK

Serial Clock Digital Input Pin

SDO/RDY

Data/Ready Digital Output Pin

7CS

Chip Select Digital Input Pin

8VDD

Positive Supply Voltage Pin

Type Identification: I = Input; O = Output; P = Power

MCP3550 Datasheet(PDF) 13 Page - Microchip Technology

MCP3550 Datasheet(HTML) 13 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL