ACT8828 datasheet(14/49 Pages) ACTIVE-SEMI

14 / 49 page

SYSTEM MANAGEMENT

ACT8828

Rev 3, 24-Sep-09

Active-Semi

Innovative Power

- 14 -

www.active-semi.com

ActivePMU

TM and ActivePathTM are trademarks of Active-Semi.

2CTM is a trademark of Philips Electronics.

Thermal Shutdown

The

ACT8828

integrates

thermal

shutdown

protection circuitry to prevent damage resulting

from excessive thermal stress, as may be

encountered under fault conditions. This circuitry

disables all regulators if the ACT8828 die

temperature exceeds 160°C, and prevents the

regulators from being enabled until the IC

temperature drops by 20°C (typ).

Control Sequence

Sequence A

The ACT8828QJ1## features a flexible enable

architecture that allows it to support a variety of

push-button enable/disable schemes. Although

other startup routines are possible, a typical startup

and shutdown process proceeds as shown in

Figure 3.

System startup is initiated whenever the following

conditions occurs:

1) nPBIN is pushed low via 100kΩ resistance,

When condition exists, the ACT8828QJ1## begins

its system startup procedure by enabling REG1.

When REG1 reaches regulation, REG2 and REG3

are enable, and nRSTO is asserted low, holding the

microprocessor in reset for a user selectable reset

period of 260ms. If VOUT1 is within 6% of its

regulation voltage when the reset timer expires, the

nRSTO is de-asserted, and the microprocessor can

begin its power-up sequence. Once the power-up

routine is successfully completed, the system

remains enabled after the push-button is released

as long as the microprocessor asserts any one of

ON1, ON2, ON3, or ON4. ON1, ON2, ON3, or ON4

enable REG1, REG2, REG3 and REG4 separately,

but any one of them can enable ACT8828QJ1##.

This

start-up

procedure

requires

that

the

pushbutton be held until the microprocessor

assumes control (by asserting any one of ON1,

ON2, ON3, and ON4), providing protection against

inadvertent

momentary

assertions

the

pushbutton. If desired, longer “push-and-hold” times

can be easily implemented by simply adding an

additional time delay before asserting ON1, ON2,

ON3, or ON4. If the microprocessor is unable to

complete its power-up routine successfully before

the

user

lets

the

push-button,

the

ACT8828QJ1## automatically shuts itself down.

This

start-up

procedure

requires

that

the

pushbutton be held until the microprocessor

assumes control (by asserting any one of ON1,

ON2, ON3, and ON4), providing protection against

inadvertent

momentary

assertions

the

pushbutton. If desired, longer “push-and-hold” times

can be easily implemented by simply adding an

additional time delay before asserting ON1, ON2,

ON3, or ON4. If the microprocessor is unable to

complete its power-up routine successfully before

the

user

lets

the

push-button,

the

ACT8828QJ1## automatically shuts itself down.

Once a successful power-up routine is completed, a

shutdown process may be initiated by asserting

nPBIN a second time, typically as the result of

pressing the push-button. Although the shutdown

process is completely software-controlled, a typical

shutdown sequence proceeds as follows: The

second assertion of nPBIN asserts nPBIN and

interrupts the microprocessor, which then initiates

an interrupt service routine to reveal that nPBIN has

been asserted. The microprocessor disables each

regulator according to the sequencing requirements

of the system, then the system will finally be

disabled when ON1, ON2, ON3, and ON4 have

been de-asserted.

Figure 3:

Sequence A

Sequence B

The ACT8828QJ2## features a flexible enable

architecture that allows it to support a variety of

push-button enable/disable schemes. Although

other startup routines are possible, a typical startup

FUNCTIONAL DESCRIPTION CONT’D

94% of VOUT1

nPBIN

System Enable

OUT1

Enable Qualification

OUT2, OUT3

~100ms

First Push

Button

Assert

Power-Hold

Second Push

Button

Release

Button

System

Shutdown

OUT4

260ms

ON1, ON2, ON3, ON4

nRSTO

nIRQ

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